Methods, systems, and computer program product for parallelizing tasks in processing an electronic circuit design
Granted: April 9, 2013
Patent Number:
8418094
Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform…
System and method for simulating a transmission gate network and a bi-directional connect module within an analog and mixed-signal circuit
Granted: April 9, 2013
Patent Number:
8417505
The present invention provides systems and methods for simulating an analog and mixed-signal circuit design comprising an analog circuit segment and a transmission gate network of a digital circuit segment, where the analog circuit segment is connected to the transmission gate network using a bi-directional connect module, where the analog circuit segment contributes with its own driving force to the digital circuit segment as an equivalent to a driver, and where the digital circuit…
Method and mechanism for performing region query using hierarchical grids
Granted: April 2, 2013
Patent Number:
8413093
Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further…
Temporal decomposition for design and verification
Granted: April 2, 2013
Patent Number:
8413090
Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the…
Verification plans to merging design verification metrics
Granted: April 2, 2013
Patent Number:
8413088
A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for…
Method and mechanism for implementing region query using hierarchical grids
Granted: April 2, 2013
Patent Number:
8413087
Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further…
Full subtractor cell for synthesis of area-efficient subtractor and divider
Granted: March 26, 2013
Patent Number:
8407277
A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first…
System and method for automatic extraction of power intent from custom analog/custom digital/mixed signal schematic designs
Granted: March 26, 2013
Patent Number:
8407635
A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with…
Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing
Granted: March 26, 2013
Patent Number:
8407630
A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more…
Method and system for context-specific mask inspection
Granted: March 26, 2013
Patent Number:
8407627
A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
Method and mechanism for maintaining existence information for electronic layout data
Granted: March 26, 2013
Patent Number:
8407228
Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further…
Method and system for generating verification information and tests for software
Granted: March 19, 2013
Patent Number:
8402438
Disclosed is a process, system, and computer program product for generating a verification test or verification environment for testing and verifying software or mixed software/hardware. Object code is analyzed to generate and setup test information and environments. The object code is analyzed to identify information about the software important or relevant for the verification process. Based upon the information generated from the object code, one or more verification environments or…
Method and system for subnet defect diagnostics through fault compositing
Granted: March 19, 2013
Patent Number:
8402421
A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The…
Spine selection mode for layout editing
Granted: March 19, 2013
Patent Number:
8402417
Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a…
Methods and systems for analog object fetch in mixed-signal simulation
Granted: March 19, 2013
Patent Number:
8401828
Systems and methods for simulating and verifying an analog mixed signal design provide an analog mixed signal testbench configured to verify analog parameters of the design. The testbench can include a mechanism to fetch a value of an analog object in an analog portion of a mixed signal design. The testbench mechanism can include an argument specifying the name of the object and the analog quantity to be fetched for that object. The testbench can retrieve estimated values and can further…
Method and system for identifying power defects using test pattern switching activity
Granted: March 12, 2013
Patent Number:
8397113
A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and failure test patterns are identified from the plurality of test patterns by comparing the test result with the predicted test result. A switching activity count is obtained for each of the plurality of test patterns. Based on the switching activity count, ranks for each of the plurality of test…
Layout versus schematic error system and method
Granted: March 12, 2013
Patent Number:
8397194
According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the…
Method and apparatus to use physical design information to detect IR drop prone test patterns
Granted: March 5, 2013
Patent Number:
8392868
A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet…
Method and system for model-based routing of an integrated circuit
Granted: March 5, 2013
Patent Number:
8392864
Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.
Frequency adjustment in a control system
Granted: February 26, 2013
Patent Number:
8384453
The present disclosure relates to a method, apparatus, and system for locking a phase locked loop (PLL). The method may include receiving a reference signal at a phase locked loop (PLL) circuitry having a first PLL circuitry and a second PLL circuitry. The first PLL circuitry may include a fixed frequency oscillator. The method may further include adjusting a division ratio using, at least in part, a fractional divider circuitry in communication with the fixed frequency oscillator, to…
