Program thread selection between a plurality of execution pipelines
Granted: December 20, 2022
Patent Number:
11531550
Techniques are disclosed relating to an apparatus that includes a plurality of execution pipelines including first and second execution pipelines, a shared circuit that is shared by the first and second execution pipelines, and a decode circuit. The first and second execution pipelines are configured to concurrently perform operations for respective instructions. The decode circuit is configured to assign a first program thread to the first execution pipeline and a second program thread…
Switching power aware driver resizing by considering net activity in buffering algorithm
Granted: December 13, 2022
Patent Number:
11526650
A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current…
Method and system for assertion-based formal verification using unique signature values
Granted: December 6, 2022
Patent Number:
11520964
A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version…
Pruning of buffering candidates for improved efficiency of evaluation
Granted: December 6, 2022
Patent Number:
11520959
An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering…
Systems and methods for intercycle gap refresh and backpressure management
Granted: December 6, 2022
Patent Number:
11520531
A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed…
Cell-width aware buffer insertion technique for narrow channels
Granted: November 29, 2022
Patent Number:
11514222
An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining…
System and method for assertion-based formal verification using cached metadata
Granted: November 29, 2022
Patent Number:
11514219
The present disclosure relates to a system and method for assertion-based formal verification in an electronic design environment. Embodiments may include executing, using a processor, an assertion-based formal verification proof process on a model of an electronic design and analyzing a first property associated with the model. Embodiments may further include generating at least one trace of the first property and determining a mapping function associated with the first property.…
System and method for performing static timing analysis of electronic circuit designs using a tag-based approach
Granted: November 29, 2022
Patent Number:
11514218
Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.
Method, product, and system for integrating a hardware accelerator with an extensible processor
Granted: November 29, 2022
Patent Number:
11513818
An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a…
Systems and methods for signal observability rating
Granted: November 22, 2022
Patent Number:
11507720
This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a…
Applying a hierarchical proof to formal verification based path sensitization
Granted: November 22, 2022
Patent Number:
11507492
The present disclosure relates to a method for electronic design verification. Embodiments may include identifying a plurality of higher level instances along an electronic design path from a source to a destination. Embodiments may further include analyzing inter-instance path information associated with the plurality of higher level instances included in the electronic design path from source to destination. Analyzing may include ignoring information included within the plurality of…
Circuit for fast interrupt handling
Granted: November 22, 2022
Patent Number:
11507414
A circuit for fast interrupt handling is disclosed. An apparatus includes a processor circuit having an execution pipeline and a table configured to store a plurality of pointers that correspond to interrupt routines stored in a memory circuit. The apparatus further includes an interrupt redirect circuit configured to receive a plurality of interrupt requests. The interrupt redirect circuit may select a first interrupt request among a plurality of interrupt requests of a first type. The…
Systems and methods for modeling interactions of power and signals in a multi-layered electronic structure
Granted: November 15, 2022
Patent Number:
11501049
The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling…
System and method for decoupling capacitor selection and placement using genetic optimization
Granted: November 15, 2022
Patent Number:
11501044
Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more…
Method, system, and computer program product for implementing electronic design closure with reduction techniques
Granted: November 8, 2022
Patent Number:
11494540
Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure…
Post simulation debug and analysis using a system memory model
Granted: November 1, 2022
Patent Number:
11487561
According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register…
Hardware efficient decision feedback equalization training
Granted: October 25, 2022
Patent Number:
11483185
Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by…
Slew rate boosting for communication interfaces
Granted: October 25, 2022
Patent Number:
11481148
This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay…
Emulator synchronization subsystem with enhanced slave mode
Granted: October 18, 2022
Patent Number:
11474844
Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a…
Methods and apparatus for buffered assertion reporting in emulation
Granted: October 18, 2022
Patent Number:
11475192
Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host…
