Method and apparatus for job pre-scheduling by distributed job manager in a digital multi-processor system
Granted: April 28, 2020
Patent Number:
10635497
A method and a system embodying the method for job pre-scheduling in a processing system comprising distributed job management, encompassing: determining a maximum amount of pre-schedulable jobs for each of a plurality of engines; setting for each of the plurality of engines a threshold less than or equal to the maximum amount; pre-scheduling by a scheduler an amount of jobs less than or equal to the threshold to at least one of a plurality of job managers; determining at the at least…
Methods and systems for generating interrupts by a response direct memory access module
Granted: April 21, 2020
Patent Number:
10628350
Methods and systems for generating interrupts are provided. One method includes maintaining an in-pointer array by a response direct memory access (DMA) module of an adapter indicating that a message has been posted at a host memory of a host system coupled to the adapter for sending and receiving data using a network; updating an out-pointer array at the response DMA module by a host system processor, after the host system processor reads the message posted at the host memory; receiving…
Method of handling large protocol layers for configurable extraction of layer information and an apparatus thereof
Granted: April 7, 2020
Patent Number:
10616380
Embodiments of the apparatus for handling large protocol layers relate to an implementation that optimizes a field selection circuit. This implementation provides software like flexibility to a hardware parser engine in parsing packets. The implementation limits a size of each layer and splits any layer that exceeds that size into smaller layers. The parser engine extracts data from the split layers just as it would from a non-split layer and, then, concatenates the extracted data in a…
Packet processing system, method and device having reduced static power consumption
Granted: April 7, 2020
Patent Number:
10616144
A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.
Method and apparatus for multi-band voltage-controlled oscillator (VCO) band selection
Granted: April 7, 2020
Patent Number:
10615746
A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal…
Admission control for memory access requests
Granted: March 24, 2020
Patent Number:
10599577
Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of…
Managing lock and unlock operations using operation prediction
Granted: March 24, 2020
Patent Number:
10599430
Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions…
Methods and systems for tracking a virtual memory of a virtual machine
Granted: March 17, 2020
Patent Number:
10592271
Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while…
Method and system for ordering I/O access in a multi-node environment
Granted: March 17, 2020
Patent Number:
10592459
According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of synchronizing access to an input/output (I/O) device in the multi-chip system comprises initiating, by a first agent of the multi-chip system, a first operation for accessing the I/O device, the first operation is queued, prior to execution by the I/O…
Low latency interconnect protocol for coherent multi-chip communication
Granted: March 17, 2020
Patent Number:
10592452
In one embodiment, a data message is generated at a first system-on-chip (SOC) for transmission to a second SOC. A stream of data words is generated from the data message, the data words alternating between even and odd data words. Each data word in the stream of data words is divided into a first pattern of slices for even data words and a second pattern of slices for odd data words, with the slices distributed across plural output ports at the first SOC. At each output port, two slices…
Method and apparatus for uplink control channel detection
Granted: March 10, 2020
Patent Number:
10587388
Methods and apparatus for uplink control channel detection. In an exemplary embodiment, a method includes generating Top-Q Channel Quality Indicator (CQI) candidates from information received over an uplink control channel, generating a CQI symbol for each of the Top-Q CQI candidates, and generating a CQI energy metric from the CQI symbols. If the uplink control channel is formatted in format 2, then performing operations of combining the CQI energy metric with a pilot energy metric to…
Barrel compactor system, method and device
Granted: March 3, 2020
Patent Number:
10581455
A packet processing system having a barrel compactor that extracts a desired data subset from an input dataset (e.g. an incoming packet). The barrel compactor is able to selectively shift one or more of the input data units of the input dataset based on individual shift values for those data units. Additionally, in some embodiments one or more of the data units are able to be logically combined to produce a desired logical output unit.
Method of implementing a network ASIC in a network device
Granted: March 3, 2020
Patent Number:
10579573
Embodiments of the present invention are directed to a configuration interface of a network ASIC. The configuration interface allows for two modes of traversal of nodes. The nodes form one or more chains. Each chain is in a ring or a list topology. A master receives external access transactions. Once received by the master, an external access transaction traverses the chains to reach a target node. A target node either is an access to a memory space or is a module. A chain can include at…
Method and apparatus for bypass routing of multicast data packets and avoiding replication to reduce overall switch latency
Granted: February 18, 2020
Patent Number:
10567273
An apparatus for routing multicast data packets, the apparatus includes an ingress port to receive data streams of multicast data packets and status data about egress ports available to transmit the multicast traffic data streams. A processor coupled to the ingress port, to identify source data of the multicast data packets of the data streams to match the multicast data packets with available egress ports. The processor to determine, using the identified source and status data which of…
Method of dynamically renumbering ports and an apparatus thereof
Granted: February 11, 2020
Patent Number:
10560399
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total…
Managing memory access requests with prefetch for streams
Granted: February 11, 2020
Patent Number:
10558577
Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or…
Methods and systems for distributing memory requests
Granted: February 11, 2020
Patent Number:
10558573
A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed…
Methods and apparatus for frequency offset estimation
Granted: February 4, 2020
Patent Number:
10554469
Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary…
Method and apparatus for providing a low latency transmission system using adjustable buffers
Granted: January 7, 2020
Patent Number:
10530826
One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example,…
Phantom queue link level load balancing system, method and device
Granted: December 31, 2019
Patent Number:
10523567
A data processing system includes a phantom queue for each of a plurality of output ports each associated with an output link for outputting data. The phantom queues receive/monitor traffic on the respective ports and/or the associated links such that the congestion or traffic volume on the output ports/links is able to be determined by a congestion mapper coupled with the phantom queues. Based on the determined congestion level on each of the ports/links, the congestion mapper selects…
