Managing synonyms in virtual-address caches
Granted: September 26, 2017
Patent Number:
9772943
A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a…
Method and apparatus for quantizing soft information using linear quantization
Granted: September 19, 2017
Patent Number:
9768912
A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The…
Reverse NFA generation and processing
Granted: September 12, 2017
Patent Number:
9762544
In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input…
Session based packet mirroring in a network ASIC
Granted: September 12, 2017
Patent Number:
9760418
A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a…
Input output value prediction with physical or virtual addressing for virtual environment
Granted: September 5, 2017
Patent Number:
9753859
Method and system embodying the method for input/output value determination at a processor core, comprising generating an I/O instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of I/O devices addresses. When the comparing is successful determining the I/O device or a state on the I/O device to receive the I/O instruction in accordance with the address; setting a value of a first register to a value identifying the determined…
Packet processing system, method and device to optimize packet buffer space
Granted: August 29, 2017
Patent Number:
9747226
A buffer logic unit of a packet processing device that is configured to allocate single pages to two or more packets if the current packets stored on the page do not fully fill the single page and to store and maintain page slot specific page state data for each of the packet data stored on the pages.
Flexible instruction execution in a processor pipeline
Granted: August 29, 2017
Patent Number:
9747109
Executing instructions in a processor includes analyzing operations to be performed by instructions, including: determining a latency associated with a first operation to be performed by a first instruction, determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and assigning a value to the second instruction corresponding to the determined latency associated with the first operation. One…
Method of dynamically renumbering ports and an apparatus thereof
Granted: August 22, 2017
Patent Number:
9742694
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total…
Method to measure edge-rate timing penalty of digital integrated circuits
Granted: August 22, 2017
Patent Number:
9740807
Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing…
Method for storing and retrieving packets in high bandwidth and low latency packet processing devices
Granted: August 15, 2017
Patent Number:
9736069
A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.
Lookup front end packet input processor
Granted: August 8, 2017
Patent Number:
9729527
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Apparatus and method for processing alternately configured longest prefix match tables
Granted: August 8, 2017
Patent Number:
9729447
A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an…
Fast hardware switchover in a control path in a network ASIC
Granted: August 8, 2017
Patent Number:
9729338
A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the…
Apparatus and method for software enabled access to protected hardware resources
Granted: August 8, 2017
Patent Number:
9729320
A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key.
Method and apparatus for aligning signals
Granted: August 1, 2017
Patent Number:
9721627
A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation,…
Managing reuse information in caches
Granted: August 1, 2017
Patent Number:
9720773
Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse…
Method and apparatus for power control
Granted: July 11, 2017
Patent Number:
9703351
Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power.
Apparatus and method for media access control scheduling with a priority calculation hardware coprocessor
Granted: July 11, 2017
Patent Number:
9706564
An apparatus includes a Media Access Control (MAC) scheduler to generate a priority value calculation request with a specified formula and a list of metrics. A hardware based priority value calculation coprocessor services the priority value calculation request in accordance with the specified formula and the list of metrics.
Method and system for compressing data for a translation look aside buffer (TLB)
Granted: July 11, 2017
Patent Number:
9703722
An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed…
Apparatus and method for distributed instruction trace in a processor system
Granted: July 11, 2017
Patent Number:
9703669
One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to…
