Method and an apparatus for work request arbitration in a network processor
Granted: December 5, 2017
Patent Number:
9838471
A method and a system embodying the method for work request arbitration, comprising receiving a work request, the work request indicating one or more groups from a plurality of groups; determining at least one of a plurality of parameters in accordance with the received work request; determining eligibility to provide work among the one or more groups that have work in a work queue in accordance with a first set of the plurality of parameters; and selecting one of the determined eligible…
Protocol independent programmable switch (PIPS) software defined data center networks
Granted: November 21, 2017
Patent Number:
9825884
A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs,…
Method and apparatus for discarding unused points from constellation mapping rule using transceiver processing hardware (“TPH”)
Granted: November 21, 2017
Patent Number:
9825799
An aspect of present invention discloses a transceiver processing hardware (“TPH”) which is configured to process wireless information based on a constellation map. The TPH includes a minimum mean square error (“MMSE”), an inverse discrete Fourier transform (“IDFT”), and a demapper. The MMSE provides estimation of received bit stream, and the IDFT generates a list of samples associated with frequency of the bit stream. The demapper configured to discard unused constellation…
Bypass FIFO for multiple virtual channels
Granted: November 21, 2017
Patent Number:
9824058
A group of low-level FIFOs may be logically bound together to form a super-FIFO. The super-FIFO may treat each low-level FIFO as a storage location. The super-FIFO may enable a push to (or a pop from) every low-level FIFO, simultaneously. The super-FIFO may enable a virtual channel (VC) to use the super-FIFO, bypassing a VC FIFO for the VC, removing several cycles of latency otherwise needed for enqueuing and dequeuing messages in the VC FIFO. In addition, the super-FIFO may enable…
Apparatus and method for parallel CRC units for variably-sized data frames
Granted: November 21, 2017
Patent Number:
9823960
A cyclic redundancy check (CRC) device configured to support parallel calculation of a CRC value for a data frame comprises a plurality of CRC processing units each configured to accept one of a plurality of data segments of the data frame of a variable size that can be unknown to the CRC device beforehand and generate one of plurality of partial CRC values in parallel with rest of the CRC processing units over multiple clock cycles/iterations. The CRC device further comprises an…
Memory management for finite automata processing
Granted: November 21, 2017
Patent Number:
9823895
Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite…
Method and apparatus for virtualization
Granted: November 21, 2017
Patent Number:
9823868
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to…
Systems and methods for supporting hot plugging of remote storage devices accessed over a network via NVME controller
Granted: November 14, 2017
Patent Number:
9819739
A new approach is proposed that contemplates systems and methods to support hot plugging and/or unplugging one or more of remote storage devices virtualized as extensible/flexible storages and NVMe namespace(s) via an NVMe controller during operation. First, the NVMe controller virtualizes and presents a set of remote storage devices to one or more VMs running on a host attached to the NVMe controller as logical volumes in the NVMe namespace(s) so that each of the VMs running on the host…
Testbench builder, system, device and method including latency detection
Granted: November 14, 2017
Patent Number:
9817067
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…
Method and system for improved load balancing of received network traffic
Granted: November 7, 2017
Patent Number:
9813342
A method and a system embodying the method for load balancing of a received a packet based network traffic, comprising: receiving a packet at a software defined network switch; determining information pertaining to uniqueness of a packet flow for the received packet; providing the determined information and the received packet to a network interface controller; and processing the received packet at the network interface controller in accordance with the provided determined information,…
Hierarchical hardware linked list approach for multicast replication engine in a network ASIC
Granted: November 7, 2017
Patent Number:
9813327
A multicast rule is represented in a hierarchical linked list with N tiers. Each tier or level in the hierarchical linked list corresponds to a network layer of a network stack that requires replication. Redundant groups in each tier are eliminated such that the groups in each tier are stored exactly once in a replication table. A multicast replication engine traverses the hierarchical linked list and replicates a packet according to each node in the hierarchical linked list.
Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor
Granted: November 7, 2017
Patent Number:
9811467
A method and a system embodying the method for pre-fetching and processing work for processor cores in a network processor, comprising requesting pre-fetch work by a requestor; determining that the work may be pre-fetched for the requestor; searching for the work to pre-fetch; and pre-fetching the found work into one of one or more pre-fetch work-slots associated with the requestor is disclosed.
Determination of flip-flop count in physical design
Granted: October 17, 2017
Patent Number:
9792400
System and method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design. The outputs of each logic block are defined as primary inputs, and the inputs of each logic block are defined as primary outputs. Each interconnect is traversed from a primary input a primary output to identify the flip-flops and determine the flip-flop count. If an interconnect has a greater flip-flop count than an RTL estimated count, measures are taken to…
Graph caching
Granted: October 10, 2017
Patent Number:
9787693
In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is…
Engine architecture for processing finite automata
Granted: October 10, 2017
Patent Number:
9785403
An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at…
System and method for low-latency multimedia streaming
Granted: October 3, 2017
Patent Number:
9781477
Systems and methods for transmitting a multimedia stream over a communication link on a network are disclosed. The systems and methods adaptively adjust encoding parameters based on monitoring changing conditions of the network. A transmitter includes an adaptive-rate encoder that adaptively adjusts a video encoding bit rate in response to changing conditions of the communication link. The encoder maintains tight rate control by utilizing slice processing and sub-frame rate adaptation,…
Managing translation invalidation
Granted: October 3, 2017
Patent Number:
9779028
Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists…
Testbench builder, system, device and method having agent loopback functionality
Granted: October 3, 2017
Patent Number:
9778315
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…
Managing synonyms in virtual-address caches
Granted: September 26, 2017
Patent Number:
9772943
A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a…
Method and system for compressing data for a translation look aside buffer (TLB)
Granted: September 26, 2017
Patent Number:
9772952
An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed…
