Method of using a unique packet identifier to identify structure of a packet and an apparatus thereof
Granted: November 15, 2016
Patent Number:
9497294
Embodiments of the apparatus for modifying packet headers relate to a packet generalization scheme that maintains information across protocol layers of packets. The packet generalization scheme uses a protocol table that includes layer information for all possible protocol layer combinations. The protocol layer combinations in the protocol table are manually configured through software. Each protocol layer combination in the protocol table is uniquely identified by a PktID. A rewrite…
Lookup front end packet output processor
Granted: November 15, 2016
Patent Number:
9497117
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Method and apparatus for reference voltage calibration in a single-ended receiver
Granted: November 15, 2016
Patent Number:
9496012
According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the…
Traversal with arc configuration information
Granted: November 15, 2016
Patent Number:
9495479
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the…
Look-aside processor unit with internal and external access for multicore processors
Granted: November 8, 2016
Patent Number:
9491099
A method and a system embodying the method for information lookup request processing at a look-aside processor unit entailing storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet is a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a…
CDR voter with improved frequency offset tolerance
Granted: November 8, 2016
Patent Number:
9490968
An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a…
Auto-blow memory repair
Granted: November 8, 2016
Patent Number:
9490033
In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation…
Apparatus and method for scalable and flexible table search in a network switch
Granted: November 1, 2016
Patent Number:
9485179
A network switch comprises a packet processing pipeline including a plurality of packet processing clusters configured to process a received packet through multiple packet processing stages based on table search/lookup results. The network switch further includes a plurality of search logic units each corresponding one of the plurality of packet processing clusters, wherein each of the search logic units is configured to convert a unified search request of a table from its corresponding…
Method and apparatus for power gating hardware components in a chip device
Granted: November 1, 2016
Patent Number:
9483100
According to at least one example embodiment, a semiconductor device is configured to gate power supply to a hardware component through a transistor coupled to the hardware component. The transistor is operated by a controller in a manner to limit electric current dissipated to the hardware component during a transition period. The controller is configured to gradually turn on, or off, the hardware component during a transition period by controlling at least one input signal to the…
Method of representing a generic format header using continuous bytes and an apparatus thereof
Granted: October 18, 2016
Patent Number:
9473601
Embodiments of the apparatus for modifying packet headers relate to a rewrite engine that represents each protocol header of packets in a generic format specific to that protocol to enable programmable modifications of packets, resulting in hardware and software flexibility in modifying packet headers. Software programs generic formats in a hardware table for various protocols. The rewrite engine is able to detect missing fields from a protocol header and is able to expand the protocol…
Managing address-independent page attributes
Granted: October 18, 2016
Patent Number:
9471509
At least one CPU is configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. At the second access level, translating uses mappings in a first page table; and, at the second access level, class information is determined for a memory page mapped by the first page table based on a classification of virtual addresses. At the first access level, translating uses mappings in a second page table; and, at the first access level,…
Partitioned error code computation
Granted: October 18, 2016
Patent Number:
9471416
A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such…
Testing semiconductor devices
Granted: October 18, 2016
Patent Number:
9470719
An apparatus includes a plurality of semiconductor devices and an electrical input device for applying voltage to the plurality of semiconductor devices. There is a switching array configured to sequentially interconnect the electrical input device to each of the semiconductor devices and disconnect the other semiconductor devices from the electrical input device. The semiconductor device connected to the electrical input device is a device under test that produces a test current and the…
Processor with efficient work queuing
Granted: October 11, 2016
Patent Number:
9465662
Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor.
Apparatus and method for interrupt collecting and reporting status and delivery information
Granted: October 4, 2016
Patent Number:
9460033
A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt delivery information in a first structure; storing for each of the at least one interrupt at least an indicator of one or more entities to execute an interrupt handler routine in a second structure; and reporting one of the at least one interrupt to the one or more entities to execute an interrupt…
Low latency rate control system and method
Granted: September 13, 2016
Patent Number:
9445107
An encoder within a video transmission system controls the bit allocation at a sub-frame level. A frame is divided into smaller blocks, known as rate control blocks. Rate control blocks are used as the basic unit for bit allocation. This bit allocation achieves the target bit rate desired by the system as well as meet latency constraints. The encoder uses the slice partitioning capabilities to generate the rate control blocks using one or more slices of the image frame. This feature…
System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks
Granted: September 13, 2016
Patent Number:
9443053
Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution…
Method of forming a hash input from packet contents and an apparatus thereof
Granted: September 6, 2016
Patent Number:
9438703
Embodiments of the apparatus for forming a hash input from packet contents relate to a programmable flexible solution to form hash inputs, allowing for hardware changes and for adding support for newer protocols as and when they are defined in the future. A packet is split into individual layers. Each layer is given a unique layer type number that helps identify what that layer is. Based on the layer type, each layer is expanded to a generic format. Each layer has a set of hash commands…
Processing of finite automata based on a node cache
Granted: September 6, 2016
Patent Number:
9438561
Nodes of a per-pattern NFA may be stored amongst one or more of a plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels. At least one processor may be configured to cache one or more nodes of the per-pattern NFA in the node cache based on a cache miss of a given node of the one or more nodes and a hierarchical node…
Systems and methods for supporting migration of virtual machines accessing remote storage devices over network via NVMe controllers
Granted: August 30, 2016
Patent Number:
9430268
A new approach is proposed virtual machines (VMs) accessing remote storage devices over a network via non-volatile memory express (NVMe) controllers to migrate live from a current host to a destination host. A first virtual NVMe controller running on a first physical NVMe controller enables a first VM running on the current host to perform storage operations to logical volumes mapped to the remote storage devices over the network as if they were local storage volumes. During VM…
