Method and an apparatus for virtualization of a quality-of-service
Granted: June 28, 2016
Patent Number:
9379992
A method and a system embodying the method for virtualization of a quality of service, comprising associating a packet received at an interface with an aura via an aura identifier; determining configuration parameters for the aura; determining a pool for the aura; determining the state of the pool resources, the resources comprising a level of buffers available in the pool and a level of buffers allocated to the aura; and determining a quality of service for the packet in accordance with…
Apparatus and method of generating lookups and making decisions for packet modifying and forwarding in a software-defined network engine
Granted: June 28, 2016
Patent Number:
9379963
Embodiments of the present invention relate to a Lookup and Decision Engine (LDE) for generating lookup keys for input tokens and modifying the input tokens based on contents of lookup results. The input tokens are parsed from network packet headers by a Parser, and the tokens are then modified by the LDE. The modified tokens guide how corresponding network packets will be modified or forwarded by other components in a software-defined networking (SDN) system. The design of the LDE is…
Inter-chip interconnect protocol for a multi-chip system
Granted: June 21, 2016
Patent Number:
9372800
A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory…
Co-verification—of hardware and software, a unified approach in verification
Granted: June 21, 2016
Patent Number:
9372772
A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.
Virtualized network interface for TCP reassembly buffer allocation
Granted: June 7, 2016
Patent Number:
9363193
A method and a system embodying the method for dynamically allocating context for Transmission Control Protocol (TCP) reassembly, comprising providing a fixed plurality of global common TCP contexts; reserving for each of one or more virtual network interface card(s) one or more TCP context(s) out of the fixed plurality of the global common TCP contexts; and allocating to a virtual network interface card from the one or more virtual network interface card(s) a TCP context from the…
System and method for automated functional coverage generation and management for IC design protocols
Granted: May 31, 2016
Patent Number:
9355206
A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited…
Variable strobe for alignment of partially invisible data signals
Granted: May 24, 2016
Patent Number:
9349434
A method of sampling data signals in response to a timing signal includes receiving data signals that are skewed relative to each other. Each data signal has a valid-data window having an extent such that, when a data signal is received, an invisible portion of the valid-data window is outside an observation window and a visible portion of the valid-data window is inside the observation window. The method further includes, for each of the data signals, identifying a designated location…
System and method for rule matching in a processor
Granted: May 17, 2016
Patent Number:
9344366
In one embodiment, a system includes a format block configured to receive a key, at least one rule, and rule formatting information. The rule can have one or more dimensions. The format block can be further configured to extract each of the dimensions from the at least one rule. The system can further include a plurality of dimension matching engines (DME). Each DME can be configured to receive the key and a corresponding formatted dimension, and process the key and the corresponding…
Clock distribution circuit with distributed delay locked loop
Granted: May 10, 2016
Patent Number:
9335784
In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further…
Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process
Granted: May 10, 2016
Patent Number:
9336328
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different…
Testbench builder, system, device and method including a dispatcher
Granted: May 3, 2016
Patent Number:
9330227
A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic…
Multi-core interconnect in a network processor
Granted: May 3, 2016
Patent Number:
9330002
A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit…
Method and apparatus to represent a processor context with fewer bits
Granted: April 26, 2016
Patent Number:
9323715
According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the…
Method and apparatus for managing transfer of transport operations from a cluster in a processor
Granted: April 19, 2016
Patent Number:
9319316
A method and corresponding apparatus of managing transport operations between a first memory cluster and one or more other memory clusters, include selecting, at a clock cycle in the first memory cluster, at least one transport operation destined to at least one destination memory cluster, from one or more transport operations, based at least in part on priority information associated with the one or more transport operations or current states of available processing resources allocated…
Virtualized network interface for remote direct memory access over converged ethernet
Granted: April 12, 2016
Patent Number:
9313029
A method and a system embodying the method for generating an opaque data comprising a stream identifier, comprising encrypting at least part of a stream identifier with a first secret random data to provide an encrypted stream identifier; generating a digest by applying a cryptographic hash to at least the at least the part of the stream identifier; and combining the encrypted stream identifier with the digest, is disclosed Additionally, a method and a system embodying the method for…
Methods and systems for resource management in a single instruction multiple data packet parsing cluster
Granted: April 5, 2016
Patent Number:
9307057
Methods and systems are provided for operating a SIMD packet parsing cluster, wherein the cluster includes a plurality of M packet parsing engines 1 to M, and the cluster further includes a shared memory and an instruction memory storing a plurality of instructions to be performed by each of the engines, and wherein the instructions include one or more memory accessing instructions that require accessing the shared memory. The method comprises transmitting the instructions to the engines…
System and a method for a remote direct memory access over converged ethernet
Granted: April 5, 2016
Patent Number:
9306916
A method and a system embodying the method for receiving a remote direct memory access packet comprising an opaque data, a virtual address, and a payload at a virtual network interface card that generated the opaque data; reconstructing a stream identifier by separating the opaque data into an encrypted stream identifier and a first digest; decrypting the encrypted stream identifier; verifying the decrypted stream identifier using the first digest; providing the verified stream…
Multi-function delay locked loop
Granted: April 5, 2016
Patent Number:
9306584
A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells
Granted: April 5, 2016
Patent Number:
9305129
Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more…
Systems and methods for enabling access to extensible storage devices over a network as local storage via NVME controller
Granted: March 22, 2016
Patent Number:
9294567
A new approach is proposed that contemplates systems and methods to support extensible/flexible storage access in real time by virtualizing a plurality of remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol. The NVMe controller exports and presents the remote storage devices to one or more VMs running on a host attached to the NVMe controller as the NVMe namespace(s), wherein these remote storage devices appear virtually as one or more…
