Data strobe generation
Granted: March 8, 2016
Patent Number:
9281034
In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the…
Packet extraction optimization in a network processor
Granted: March 1, 2016
Patent Number:
9276846
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can…
Method and system for skipping over group(s) of rules based on skip group rule
Granted: March 1, 2016
Patent Number:
9275336
A method and corresponding system for providing a skip group rule feature is disclosed. When a search for a key matches a skip group rule in a group of prioritized rules, the search skips over rules having priorities lower than the skip group rule and the search continues to a next group. A convenient example of a compiler rewrites the lower priority rules by subtracting the skip group rule from them. The subtraction includes subtracting range, exact-match, mask, and prefix fields. The…
Processing request keys based on a key size supported by underlying processing elements
Granted: February 23, 2016
Patent Number:
9268855
A packet classification system, methods, and apparatus are provided for packet classification. A processor of a router coupled to a network processes data packets received from a network. The processor creates a request key using information extracted from a packet. The processor splits the request key into an n number of partial request keys if at least one predetermined criterion is met. The processor also sends a non-final request that includes an i-th partial request key to a…
Maintenance of cache and tags in a translation lookaside buffer
Granted: February 23, 2016
Patent Number:
9268694
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Messaging with flexible transmit ordering
Granted: February 16, 2016
Patent Number:
9264385
In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the…
Scannable flop with a single storage element
Granted: February 16, 2016
Patent Number:
9264023
In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg. The first node of the storage element may be driven by the data leg. The opposite node of the storage element may be driven by at least one of the scan legs. The slave latch may be coupled to the master latch.
Memory interface with selectable evaluation modes
Granted: February 16, 2016
Patent Number:
9263151
A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively…
DRAM address protection
Granted: January 19, 2016
Patent Number:
9239753
In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address.
Apparatus and method for media access control scheduling with a sort hardware coprocessor
Granted: January 12, 2016
Patent Number:
9237581
An apparatus includes a Media Access Control (MAC) scheduler to generate a sort request. A hardware based sort coprocessor services the sort request in accordance with specified packet processing priority parameters to generate a sorted array.
Lookup cluster complex
Granted: December 29, 2015
Patent Number:
9225643
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response…
Multi-protocol SerDes PHY apparatus
Granted: December 22, 2015
Patent Number:
9219560
In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit…
Duplication in decision trees
Granted: December 8, 2015
Patent Number:
9208438
A packet classification system, apparatus, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure for packet classification. Duplication in the decision tree may be identified, producing a wider, shallower decision tree that may result in shorter search times with reduced…
Translation bypass in multi-stage address translation
Granted: December 8, 2015
Patent Number:
9208103
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The…
Reverse NFA generation and processing
Granted: December 1, 2015
Patent Number:
9203805
In a processor of a security appliance, an input of a sequence of characters is walked through a finite automata graph generated for at least one given pattern. At a marked node of the finite automata graph, if a specific type of the at least one given pattern is matched at the marked node, the input sequence of characters is processed through a reverse non-deterministic finite automata (rNFA) graph generated for the specific type of the at least one given pattern by walking the input…
Scope in decision trees
Granted: November 24, 2015
Patent Number:
9195939
A root node of a decision tree data structure may cover all values of a search space used for packet classification. The search space may include a plurality of rules, the plurality of rules having at least one field. The decision tree data structure may include a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. Scope in the decision tree data structure may be based on comparing a portion of the search space covered by a node to a portion of the…
Packet classification
Granted: November 17, 2015
Patent Number:
9191321
A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a security appliance coupled to a network uses a classifier table having a plurality of rules, the plurality of rules having at least one field, to build a decision tree structure including a plurality of nodes, the plurality of nodes including a subset of the plurality of rules. The methods may produce wider, shallower trees that result in shorter search…
Rule modification in decision trees
Granted: November 10, 2015
Patent Number:
9183244
A system, apparatus, and method are provided for modifying rules in-place atomically from the perspective of an active search process using the rules for packet classification. A rule may be modified in-place by updating a rule's definition to be an intersection of an original and new definition. The rule's definition may be further updated to the rule's new definition and a decision tree may be updated based on the rule's new definition. While a search processor searches for one or more…
Method and apparatus for data packet integrity checking in a processor
Granted: October 6, 2015
Patent Number:
9152494
In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection…
Method and apparatus for managing write back cache
Granted: September 22, 2015
Patent Number:
9141548
A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty…
