Multi-function delay locked loop
Granted: September 22, 2015
Patent Number:
9143140
A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.
Incremental update
Granted: September 15, 2015
Patent Number:
9137340
A system, apparatus, and method are provided for adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification. While a search processor searches for one or more rules that match keys generated from received packets, there is a need to add, delete, or modify rules. By adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification, performance and functionality…
Method and apparatus for scheduling rule matching in a processor
Granted: September 8, 2015
Patent Number:
9130819
In a network search processor, configured to handle search requests in a router, a scheduler for scheduling rule matching threads initiated by a plurality of initiating engines is designed to make efficient use of the resources in the network search processor while providing high speed performance. According to at least one example embodiment, the scheduler and a corresponding scheduling method comprise: determining a set of bundles of rule matching threads, each bundle being initiated…
Multiplexer flop
Granted: September 8, 2015
Patent Number:
9130549
In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element, a first data leg, and a second data leg. The first and second data legs may be coupled to the storage element. Clock selection logic may be coupled to the first and second data legs. The clock selection logic may have a select input for selecting between the first and second data legs. The slave latch may be coupled to the master latch.
QoS based dynamic execution engine selection
Granted: September 8, 2015
Patent Number:
9129060
In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that,…
Processor with dedicated virtual functions and dynamic assignment of functional resources
Granted: September 8, 2015
Patent Number:
9128769
In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to…
Method and an accumulator scoreboard for out-of-order rule response handling
Granted: August 18, 2015
Patent Number:
9112767
According to at least one example embodiment, a method and a corresponding accumulator scoreboard for managing bundles of rule matching threads processed by one or more rule matching engines comprise: recording, for each rule matching thread in a given bundle of rule matching threads, a rule matching result in association with a priority corresponding to the respective rule matching thread; determining a final rule matching result, for the given bundle of rule matching threads, based at…
Video encoder bit estimator for macroblock encoding
Granted: July 28, 2015
Patent Number:
9094669
A video transmission system includes an encoder to receive video images, and encode them for transfer to a decoder. The video images include macroblocks having data that are encoded according to a prediction mode, such as inter-prediction or intra-prediction. A bit estimator for the encoded macroblock within the encoder estimates a size for the encoded macroblock and predicts whether it will be an illegal size. The bit estimator applies a bit estimation function using a number of header…
Method and apparatus for amplifier offset calibration
Granted: July 21, 2015
Patent Number:
9087567
According to at least one example embodiment, a method and corresponding system for calibrating an amplifier offset include applying an input value to both input leads of an amplifier. The amplifier includes one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier. A digital value, provided as input to the DAC, is updated over a number of iterations, by a control logic coupled to the amplifier, based on an output of the amplifier. A final value of the…
Method and apparatus for multiple access of plural memory banks
Granted: June 23, 2015
Patent Number:
9065860
A processor with on-chip memory including a plurality of physical memory banks is disclosed. The processor includes a method, and corresponding apparatus, of enabling multi-access to the plurality of physical memory banks. The method comprises selecting a subset of multiple access requests to be executed in at least one clock cycle over at least one of a number of access ports connected to the plurality of physical memory banks, the selected subset of access requests addressed to…
Messaging with flexible transmit ordering
Granted: June 23, 2015
Patent Number:
9065781
In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an…
Bit error rate impact reduction
Granted: June 23, 2015
Patent Number:
9065626
In an embodiment, a method includes receiving at a data interface a data stream having a plurality of logical communication channels. The data stream includes in succession a first data burst corresponding to one of the plurality of logical communication channels, a burst control word and a second data burst corresponding to the one or an other of the plurality of logical communication channels. The burst control word includes a first error check that protects the first data burst and…
Work request processor
Granted: June 16, 2015
Patent Number:
9059945
A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit (ODU) that provides a table having several entries, each entry storing a respective work queue entry, and a number of lists. Each of the lists may be associated with a respective processor configured to execute the work, and includes pointers to entries in the table. A pointer is added to the list based on an indication of whether…
Word boundary lock
Granted: June 16, 2015
Patent Number:
9059836
In an embodiment, a method for determining a word boundary in an incoming data stream includes initializing an N bit register with initial content, receiving a number of consecutive N bit words of the incoming data stream and processing each of the number of consecutive N bit words. The processing includes performing operations per bit position of the register, including performing an XOR operation on a corresponding received data bit and a next received data bit, performing an AND…
Systems and methods for specifying. modeling, implementing and verifying IC design protocols
Granted: June 16, 2015
Patent Number:
9058463
A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended…
System and method of compression and decompression
Granted: June 9, 2015
Patent Number:
9054729
The disclosure relates to a system and a method for hardware encoding and decoding according to the Limpel Ziv STAC (LZS) and Deflate protocols based upon a configuration bit.
Clock multiplexing and repeater network
Granted: May 26, 2015
Patent Number:
9041432
A system on chip (SOC) includes a clock generator to provide one or more on-chip reference clocks to a number of physical medium attachments (PMAs) across a common clock bus. The clock generator receives one or more external, off-chip clock lines, from which it generates the on-chip reference clocks. Each of the PMAs may operate data input/output (I/O) channels under a variety of different communications protocols, which can have common or distinct reference clock frequencies.…
Lookup front end packet input processor
Granted: May 12, 2015
Patent Number:
9031075
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Video encoder bit estimator for macroblock encoding
Granted: May 5, 2015
Patent Number:
9025665
A video transmission system includes an encoder to receive video images, and encode them for transfer to a decoder. The video images include macroblocks having data that are encoded according to a prediction mode, such as inter-prediction or intra-prediction. A bit estimator for the encoded macroblock within the encoder estimates a size for the encoded macroblock and predicts whether it will be an illegal size. The bit estimator applies a bit estimation function using a number of header…
On-demand intra-refresh for end-to end coded video transmission systems
Granted: May 5, 2015
Patent Number:
9025672
A video transmission system includes an encoder and a decoder. Data may be lost during video encoding and transmission, which leads to errors in reconstructing the video images by the decoder. A return channel couples the encoder and decoder so that errors detected by the decoder are made available to the encoder. Depending on the percentage of the image not received, refresh operations are performed. An on-demand intra-refresh operation is done when the percentage of the image needed to…
