Low latency rate control system and method
Granted: September 9, 2014
Patent Number:
8831108
An encoder within a video transmission system controls the bit allocation at a sub-frame level. A frame is divided into smaller blocks, known as rate control blocks. Rate control blocks are used as the basic unit for bit allocation. This bit allocation achieves the target bit rate desired by the system as well as meet latency constraints. The encoder uses the slice partitioning capabilities to generate the rate control blocks using one or more slices of the image frame. This feature…
Method and apparatus for a virtual system on chip
Granted: September 2, 2014
Patent Number:
8826271
A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to…
Intelligent graph walking
Granted: August 26, 2014
Patent Number:
8819217
An apparatus, and corresponding method, for performing a search for a match of at least one expression in an input stream is presented. A graph including a number of interconnected nodes is generated. A compiler may assign at least one starting node and at least one ending node. The starting node includes a location table with node position information of an ending node and a sub-string value associated with the ending node. Using the node position information and a string comparison…
Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process
Granted: August 26, 2014
Patent Number:
8818921
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different…
Work migration in a processor
Granted: May 6, 2014
Patent Number:
8719331
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the…
Lookup front end packet input processor
Granted: April 29, 2014
Patent Number:
8711861
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Secure software and hardware association technique
Granted: March 18, 2014
Patent Number:
8677144
In an embodiment, authenticated hardware and authenticated software are cryptographically binded using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. This…
System and method for secure device key storage
Granted: February 25, 2014
Patent Number:
8661266
Disclosed are systems and methods for protecting secret device keys, such as High-bandwidth Digital Content Protection (HDCP) device keys. Instead of storing secret device keys in the plain, a security algorithm and one or more protection keys are stored on the device. The security algorithm is applied to the secret device keys and the one or more protection keys to produce encrypted secret device keys. The encrypted secret device keys are then stored either on chip or off-chip.
Synchronized clock phase interpolator
Granted: January 21, 2014
Patent Number:
8634509
A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
System and method for optimizing use of channel state information
Granted: December 31, 2013
Patent Number:
8619923
The present invention relates to a combiner, channel identifier, Orthogonal Frequency Division Multiplexing (OFDM) receiver and method for optimizing use of channel state information of a received signal. The method comprises analyzing a received signal in a time domain and extracting from the received signal characteristics of a communication channel. The method furthermore comprises determining a dynamic indicator of channel station information accuracy based on the characteristics of…
Lookup front end packet output processor
Granted: December 10, 2013
Patent Number:
8606959
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns…
Multiple core session initiation protocol (SIP)
Granted: December 3, 2013
Patent Number:
8601139
A Session Initiation Protocol (SIP) proxy server including a multi-core central processing unit (CPU) is presented. The multi-core CPU includes a receiving core dedicated to pre-SIP message processing. The pre-SIP message processing may include message retrieval, header and payload parsing, and Call-ID hashing. The Call-ID hashing is used to determine a post-SIP processing core designated to process messages between particular user pair. The pre-SIP and post-SIP configuration allows for…
Input output bridging
Granted: November 26, 2013
Patent Number:
8595401
In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet…
System and method to reduce memory access latencies using selective replication across multiple memory ports
Granted: October 15, 2013
Patent Number:
8560757
In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on…
Content search mechanism that uses a deterministic finite automata (DFA) graph, a DFA state machine, and a walker process
Granted: October 15, 2013
Patent Number:
8560475
An improved content search mechanism uses a graph that includes intelligent nodes avoids the overhead of post processing and improves the overall performance of a content processing application. An intelligent node is similar to a node in a DFA graph but includes a command. The command in the intelligent node allows additional state for the node to be generated and checked. This additional state allows the content search mechanism to traverse the same node with two different…
System and method for enabling access to a protected hardware resource
Granted: September 24, 2013
Patent Number:
8544106
Systems and methods are disclosed for enabling access to a protected hardware resource. A hardware component includes at least one protected hardware resource. A unique hardware ID and a unique cryptographically secure or randomly generated enable value (EV) are integrated in the hardware component at the time of manufacturing. At run-time, special software generates or receives from an external source an enable register (ER) value and a comparison is made with the stored enable value.…
Differential amplifier with de-emphasis
Granted: September 17, 2013
Patent Number:
8536944
A programmable current driver provides de-emphasis capability. A number of identical transmitter slices, consisting of a unit current source and a unit differential pair, are connected in parallel to the termination resistors. As the transmitter slices are identical, the current density through the differential pairs are identical, and the VDS voltages across them (as well as the VDS voltages across the unit current sources) are the same, ensuring that the current through each slice is…
Level-up shifter circuit
Granted: September 3, 2013
Patent Number:
8525572
A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity.
Differential amplifier with duty cycle compensation
Granted: August 27, 2013
Patent Number:
8519785
A differential amplifier replicates the input stage and cross-connects the inputs, so that the input-to-output delay will be balanced in an averaged sense. The outputs of each of the two input stages are then summed after an open loop delay matched inversion has taken place. The result is a reduction in the duty cycle distortion of the receiver amplifier over process voltage and temperature (PVT) variation. This is enabled by the fact that a full swing CMOS delay cell can be made to have…
State machine for deskew delay locked loop
Granted: August 20, 2013
Patent Number:
8513994
A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to…
