Input output bridging
Granted: June 25, 2013
Patent Number:
8473658
In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge…
Deterministic finite automata graph traversal with nodal bit mapping
Granted: June 25, 2013
Patent Number:
8473523
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc may also include a nodal bit map including structural information of a node to which the valid arc points to. A walker process may utilize the nodal bit map to determine if a memory access is necessary. The nodal bit map reduces the…
Lookup cluster complex
Granted: June 25, 2013
Patent Number:
8472452
A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. As a result of the rule matching, the lookup engine returns a response…
Single-ended to differential converter
Granted: June 25, 2013
Patent Number:
8471601
A single-ended to differential converter is presented. The converter may be configured to convert full-swing single-ended signals to low-swing differential signals within a single-stage, thereby reducing signal distortion. The converter may include a passive network of resistive elements, for example resistors and/or metal oxide semiconductor (MOS) devices operating in a linear region. The converter may also allow for adjustable design parameters such as a common mode, differential…
System and method of compression and decompression
Granted: June 4, 2013
Patent Number:
8456331
The disclosure relates to a system and a method for hardware encoding and decoding according to the Limpel Ziv STAC (LZS) and Deflate protocols based upon a configuration bit.
Deterministic finite automata (DFA) processing
Granted: March 5, 2013
Patent Number:
8392590
A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.
Method and system for selection of reference picture and mode decision
Granted: January 22, 2013
Patent Number:
8358699
A method, system and computer program product for the selection of reference pictures and mode decision during the motion estimation of a video sequence is disclosed. The video sequence includes a plurality of video frames. Each of the video frames includes a plurality of macroblocks. A full-pixel search is performed for each of the video frames, to calculate one or more full-pel rate distortion costs. Based on the one or more rate-distortion costs, one of the one or more modes is…
Method and apparatus for estimating overshoot power after estimating power of executing events
Granted: January 15, 2013
Patent Number:
8356194
Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the…
Compression with adjustable quality/bandwidth capability
Granted: January 8, 2013
Patent Number:
8350732
The disclosure provides a system and method to vary bandwidth/speed of a compression engine to tradeoff with compression quality. The system comprises an input port receiving a data stream having a current byte and a stream of preceding and subsequent bytes thereof; a history memory storing the stream of preceding bytes in blocks of history data an index engine having a table of keys associated to memory addresses of the blocks, the index engine accessing the table to output a plurality…
Method and apparatus for correcting linear error phase of an OFDM signal
Granted: December 25, 2012
Patent Number:
8340205
The present invention relates to a method and an apparatus for correcting linear error phase of an OFDM signal. The method includes a step of offsetting a rotation corresponding to a back-off value of the signal. The apparatus of the present invention includes a correction module for offsetting the rotation of the signal corresponding to the back-off value.
Deterministic finite automata (DFA) instruction
Granted: October 30, 2012
Patent Number:
8301788
A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of…
Deterministic finite automata (DFA) graph compression
Granted: May 15, 2012
Patent Number:
8180803
An apparatus, and corresponding method, for generating a graph used in performing a search for a match of at least one expression in an input stream is presented. The graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a designated node(s), or…
Method and apparatus for content based searching
Granted: May 8, 2012
Patent Number:
8176300
The scheduling of multiple request to be processed by a number of deterministic finite automata-based graph thread engine (DTE) workstations is processed by a novel scheduler. The scheduler may select an entry from an instruction in a content search apparatus. Using attribute information from the selected entry, the scheduler may thereafter analyze a dynamic scheduling table to obtain placement information. The scheduler may determine an assignment of the entry, using the placement…
Graph caching
Granted: December 27, 2011
Patent Number:
8086609
In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is…
Modular scaleable processing engine for accelerating variable length coding
Granted: September 6, 2011
Patent Number:
8013765
A mechanism for efficient CAVLC coding in a hardware implementation of a H.264 coder is provided. In an embodiment of the present invention, multiple modular CAVLC engines that each process one sub-macroblock of data are used. An assembler engine that combines the CAVLC-encoded sub-macroblock data from each modular CAVLC engine to form a output bit-stream is also provided.
DLL-based temperature sensor
Granted: June 14, 2011
Patent Number:
7961033
A temperature sensor includes an open-loop delay line comprising plural delay cells and a multiplexer configured to select a first number of the plural delay cells; a delay-locked loop comprising plural delay cells and a multiplexer configured to select a second number of the plural delay cells; a clock coupled to an input of the open-loop delay line and to an input of the delay-locked loop; a detector having a first input coupled to an output of the open-loop delay line and a second…
Method and apparatus for traversing a compressed deterministic finite automata (DFA) graph
Granted: May 24, 2011
Patent Number:
7949683
An apparatus, and corresponding method, for traversing a compressed graph used in performing a search for a match of at least one expression in an input stream is presented. The compressed graph includes a number of interconnected nodes connected solely by valid arcs. A valid arc of a current node represents a character match in an expression of a character associated with the current node. Arcs which are not valid may be pruned. Non-valid arcs may include arcs which point back to a…
Local scratchpad and data caching system
Granted: May 10, 2011
Patent Number:
7941585
A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be…
Method and apparatus for reducing host overhead in a socket server implementation
Granted: April 19, 2011
Patent Number:
7930349
A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the…
Packet queuing, scheduling and ordering
Granted: February 22, 2011
Patent Number:
7895431
A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the…
