Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device
Granted: December 6, 2018
Application Number:
20180351004
A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to…
SONOS ONO STACK SCALING
Granted: December 6, 2018
Application Number:
20180351003
A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and…
SYSTEM AND METHODS FOR AUDIO PATTERN RECOGNITION
Granted: December 6, 2018
Application Number:
20180350357
An example apparatus provides an input signal based on sound waves received by one or more microphones. The input signal includes a voice command component and one or more interference components. The apparatus receives audio data over one or more computer networks and the audio data corresponds to the one or more interference components. The apparatus uses the audio data to remove a portion of the one or more interference components from the input signal to generate an output signal,…
BLOCK MAPPING SYSTEMS AND METHODS FOR STORAGE DEVICE
Granted: December 6, 2018
Application Number:
20180349268
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB.…
DISTRIBUTED AND SYNCHRONIZED CONTROL SYSTEM FOR ENVIRONMENTAL SIGNALS IN MULTIMEDIA PLAYBACK
Granted: November 22, 2018
Application Number:
20180336929
A method includes providing a media dataset including media content data and environmental effects metadata defining a set of environmental events each corresponding to a media timestamp of a plurality of media timestamps. The method further includes, for each environmental event in the set of environmental events, identifying a protocol timestamp for a communication protocol, where the protocol timestamp corresponds to the media timestamp of the environmental event, and generating a…
USB Power Control Analog Subsystem Architecture
Granted: November 22, 2018
Application Number:
20180335818
A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage…
Programmable Shunt Regulator
Granted: November 22, 2018
Application Number:
20180335792
A device and method that includes a shunt regulator of a universal serial bus (USB) compatible power supply device is disclosed. The shunt regulator includes an amplifier with an output, a first input, and a second input. The shunt regulator also includes a current digital-to-analog converter (DAC) that is coupled to the first input of the amplifier and a voltage bus node. The current DAC adjusts a sink or a source current delivered at the first input of the amplifier to regulate a…
CURRENT SENSING IN A USB POWER CONTROL ANALOG SUBSYSTEM
Granted: November 22, 2018
Application Number:
20180335454
A device includes a power control analog subsystem of a universal serial bus-power delivery (USB-PD) compatible power supply device. The power control analog subsystem includes a programmable current sensing circuit and a current sense resistor coupled to the power control analog subsystem. The power control analog subsystem is configured to concurrently compare a current flow through the current sense resistor with at least three different reference values, e.g., compare a sensed…
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
Granted: November 8, 2018
Application Number:
20180323208
A method of forming a vertical non-volatile (NV) memory device such as 3-D NAND flash memory includes forming a vertical NV memory cell string within an opening disposed in a stack of alternating layers of a first layer and a second layer over a substrate, and dividing the vertical NV memory cell string into two halves with a first vertical deep trench and an isolation dielectric pillar formed in the first vertical deep trench, such that memory bit density of the divided vertical NV…
Charge Trapping Split Gate Device and Method of Fabricating Same
Granted: November 8, 2018
Application Number:
20180323314
A split gate device that includes a memory gate and a select gate disposed side by side, a dielectric structure having a first portion disposed between the memory gate and a substrate and a second portion disposed along an inner sidewall of the select gate to separate the select gate from the memory gate, and a spacer formed over the select gate along an inner sidewall of the memory gate. Other embodiments of embedded split gate devices including high voltage and low voltage transistors…
SECURITY NETWORK CONTROLLER
Granted: October 11, 2018
Application Number:
20180295111
A method includes using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus and transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus. The method includes using the authentication processing circuit, generating authentication data based on the first data and transferring the first data from the input/output control…
DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
Granted: October 11, 2018
Application Number:
20180293332
A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from…
Combined Analog Architecture and Functionality in a Mixed-Signal Array
Granted: October 11, 2018
Application Number:
20180292454
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a…
CAPACITANCE TO CODE CONVERTER WITH SIGMA-DELTA MODULATOR
Granted: October 4, 2018
Application Number:
20180284928
Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a…
ASYNCHRONOUS TRANSCEIVER FOR ON-VEHICLE ELECTRONIC DEVICE
Granted: September 27, 2018
Application Number:
20180276179
An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the…
SYSTEMS AND METHODS FOR ESTIMATING ANGLE OF ARRIVAL IN A WIRELESS DEVICE
Granted: September 20, 2018
Application Number:
20180267131
An example apparatus uses a transceiver to determine a first attribute value of a first RF signal received through a first antenna during a first period. An attribute estimator determines a second attribute value of the first RF signal received through a second antenna during the first period. Responsive to a control signal, the apparatus switches the attribute estimator from being coupled to the second antenna to being coupled to a third antenna. The apparatus then uses the transceiver…
CAPACITANCE SENSING AND INDUCTANCE SENSING IN DIFFERENT MODES
Granted: September 13, 2018
Application Number:
20180260049
An apparatus for inductive sensing or capacitive sensing is described. The apparatus may include a signal generator to output on a first terminal a first signal in a first mode and a second signal in a second mode. The apparatus may include a charge measuring circuit to receive on a second terminal a third signal in the first mode and a fourth signal in the second mode. The third signal is representative of an inductance of a sense unit coupled between the first terminal and the second…
Capacitive Fingerprint Sensor with Quadrature Demodulator and Multiphase Scanning
Granted: September 13, 2018
Application Number:
20180260600
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…
RATIOMETRIC MUTUAL-CAPACITANCE-TO-CODE CONVERTER
Granted: September 13, 2018
Application Number:
20180260076
An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance…
COMBINED INDUCTIVE SENSING AND CAPACITIVE SENSING
Granted: September 13, 2018
Application Number:
20180260050
An sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The…
