SECURITY NETWORK CONTROLLER
Granted: October 11, 2018
Application Number:
20180295111
A method includes using a direct memory access controller, transferring first data from a memory to an input/output control circuit via a first bus and transferring the first data from the input/output control circuit to an authentication processing circuit via a second bus, without using the first bus. The method includes using the authentication processing circuit, generating authentication data based on the first data and transferring the first data from the input/output control…
DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
Granted: October 11, 2018
Application Number:
20180293332
A method includes providing a design interface to design a device schematic for a programmable device and receiving a placement of graphical objects in the device schematic, wherein the graphical objects represent components that are both internal and external to the programmable device being configured. The method further includes assigning the graphical objects into one of an internal domain and an external domain and displaying, by the processing device, the graphical objects from…
Combined Analog Architecture and Functionality in a Mixed-Signal Array
Granted: October 11, 2018
Application Number:
20180292454
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manger coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a…
CAPACITANCE TO CODE CONVERTER WITH SIGMA-DELTA MODULATOR
Granted: October 4, 2018
Application Number:
20180284928
Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a…
ASYNCHRONOUS TRANSCEIVER FOR ON-VEHICLE ELECTRONIC DEVICE
Granted: September 27, 2018
Application Number:
20180276179
An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus. The device comprises a transceiver configured to: detect a baud rate clock signal and a phase difference between the baud rate clock signal and an input data signal that was generated asynchronously from the baud rate clock signal; obtain a timing from an edge of the baud rate clock signal based the phase difference; capture a value of the input data signal at the…
SYSTEMS AND METHODS FOR ESTIMATING ANGLE OF ARRIVAL IN A WIRELESS DEVICE
Granted: September 20, 2018
Application Number:
20180267131
An example apparatus uses a transceiver to determine a first attribute value of a first RF signal received through a first antenna during a first period. An attribute estimator determines a second attribute value of the first RF signal received through a second antenna during the first period. Responsive to a control signal, the apparatus switches the attribute estimator from being coupled to the second antenna to being coupled to a third antenna. The apparatus then uses the transceiver…
COMBINED INDUCTIVE SENSING AND CAPACITIVE SENSING
Granted: September 13, 2018
Application Number:
20180260050
An sense unit for inductive sensing or capacitive sensing is described. The sense unit may include a first terminal coupled to a first node, a first electrode coupled to the first node, and a second terminal. The sense unit may include a second electrode coupled to the second terminal. In a first mode, a first signal is received at the first terminal and a second signal is output on the second terminal, where the second signal may be representative of a capacitance of the sense unit. The…
NON-VOLATILE MEMORY ARRAY WITH MEMORY GATE LINE AND SOURCE LINE SCRAMBLING
Granted: September 13, 2018
Application Number:
20180261295
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with…
Capacitive Fingerprint Sensor with Quadrature Demodulator and Multiphase Scanning
Granted: September 13, 2018
Application Number:
20180260600
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…
RATIOMETRIC MUTUAL-CAPACITANCE-TO-CODE CONVERTER
Granted: September 13, 2018
Application Number:
20180260076
An embodiment of a capacitance sensing circuit includes a set of bridge switches coupled with a reference cell and a sensor cell. The set of bridge switches is configured to, over a first phase, increase a voltage difference between a first modulation capacitor and a second modulation capacitor, and over a second phase, decrease the voltage difference at a rate corresponding to a difference between a capacitance of the sensor cell and a capacitance of the reference cell. The capacitance…
CAPACITANCE SENSING AND INDUCTANCE SENSING IN DIFFERENT MODES
Granted: September 13, 2018
Application Number:
20180260049
An apparatus for inductive sensing or capacitive sensing is described. The apparatus may include a signal generator to output on a first terminal a first signal in a first mode and a second signal in a second mode. The apparatus may include a charge measuring circuit to receive on a second terminal a third signal in the first mode and a fourth signal in the second mode. The third signal is representative of an inductance of a sense unit coupled between the first terminal and the second…
SPUR CANCELLATION SYSTEM FOR MODEMS
Granted: July 19, 2018
Application Number:
20180205402
A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.
Uniformity correction method for low cost and non-rectangular touch sensor matrices
Granted: July 12, 2018
Application Number:
20180196575
A method includes storing a set of touch sense values corresponding to a measured characteristic of at least one unit cell of a plurality of unit cells of the touch array and accessing a correction matrix that defines an active region and an inactive region of the touch array. The inactive region is surrounded by the active region. The method further includes modifying touch sense values of a first subset of the plurality of unit cells that are partially within the active region defined…
Dynamic Bandwidth Selection
Granted: July 5, 2018
Application Number:
20180192329
Dynamic bandwidth selection based on environmental conditions is described. A bandwidth of a sub-bandwidth may be selected based on signal strength, channel interference, or overlap to optimize throughput and/or energy per bit. Additionally, system power level may define a communication bandwidth.
SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
Granted: July 5, 2018
Application Number:
20180191351
In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements…
PROTECTING CIRCUIT AND INTEGRATED CIRCUIT
Granted: July 5, 2018
Application Number:
20180191155
A protecting circuit includes a discharge switch, a trigger circuit, and a shunt circuit. The discharge switch is connected between a first terminal and a second terminal. The trigger circuit is connected to the discharge switch and comprises load devices, connected in series between the first terminal and the second terminal, and a first node between a first one and a second one of the load devices. The shunt circuit is connected to the trigger circuit at the first node, where the shunt…
ADJUSTABLE OVER-CURRENT DETECTOR CIRCUIT FOR UNIVERSAL SERIAL BUS (USB) DEVICES
Granted: July 5, 2018
Application Number:
20180191148
In an example embodiment, a device comprises a gate driver and a current detector circuit. The gate driver is configured to be coupled to a power switch on the VBUS line of a USB connector. The current detector circuit is configured to be coupled to the VBUS line and comprises a current sense amplifier, a reference voltage generator circuit, and a comparator. The current sense amplifier is configured to receive a pair of input voltages and to output an indicator signal responsive to the…
Suppression of Program Disturb with Bit Line and Select Gate Voltage Regulation
Granted: July 5, 2018
Application Number:
20180190361
Techniques for suppression of program disturb in flash memory devices are described herein. In an example embodiment, an apparatus comprises a flash memory device coupled to a microprocessor. The flash memory device comprises rows and columns of memory cells, where the memory cells in each row are coupled to a source line and to a select-gate (SG) line, and the memory cells in each column are coupled to a respective bit line (BL). A control circuit in the flash memory device is…
METHOD AND APPARATUS FOR DATA TRANSMISSION VIA CAPACITANCE SENSING DEVICE
Granted: July 5, 2018
Application Number:
20180188854
Example systems, methods, and apparatus transfer data to a communication device by capacitively coupling an analog signal through a capacitor formed by the capacitance sensor, of a transmitting device, and the communication device
DAMASCENE OXYGEN BARRIER AND HYDROGEN BARRIER FOR FERROELECTRIC RANDOM-ACCESS MEMORY
Granted: June 28, 2018
Application Number:
20180182770
Disclosed herein is an apparatus that includes a ferrocapacitor disposed on a damascene barrier film. The damascene barrier film includes a hydrogen barrier region and an oxygen barrier region, with each being in contact with a bottom surface of the ferrocapacitor.
