Embedded Certificate Method for Strong Authentication and Ease of Use for Wireless IoT Systems
Granted: June 28, 2018
Application Number:
20180184290
An Internet-of-Things (IoT) device and secure communication and authentication protocol is described for identifying an IoT device and counter party and ensuring that communication between the IoT device and the counter party is authenticated before transmission and receipt of data over the trusted communication pathway.
INPUT/OUTPUT MULTIPLEXER BUS
Granted: June 14, 2018
Application Number:
20180164358
One embodiment includes and I/0 bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/0 port to the signal line. Switch logic coupled to the I/0 bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/0 port.
PHASE CONTROLLER APPARATUS AND METHODS
Granted: June 14, 2018
Application Number:
20180168012
A phase controller includes a plurality of pulse width modulation (PWM) circuits, a plurality of switching devices, a computing unit, and a latency generator. The plurality of PWM circuits output pulse signals. The plurality of switching devices are coupled to the respective plurality of PWM circuits, and switch on and off based on the pulse signals. The computing unit calculates the pulse signals to be output from the plurality of PWM circuits, based on outputs of the plurality of…
Split-Gate Flash Cell formed on Recessed Substrate
Granted: June 14, 2018
Application Number:
20180166458
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed in a first region of a substrate, and a non-volatile memory (NVM) cell including a select gate and a memory gate formed in a first recess in a second region of the same substrate, wherein the recess is recessed relative to a first surface of the substrate. The metal-gate logic transistor includes a planarized surface above and substantially parallel…
INTEGRATION OF A MEMORY TRANSISTOR INTO HIGH-K, METAL GATE CMOS PROCESS FLOW
Granted: June 14, 2018
Application Number:
20180166452
A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET…
SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
Granted: June 14, 2018
Application Number:
20180166323
A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing…
NON-VOLATILE MEMORY ARRAY WITH MEMORY GATE LINE AND SOURCE LINE SCRAMBLING
Granted: June 14, 2018
Application Number:
20180166141
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with…
CAPACITIVE SENSING WITH MULTI-PATTERN SCAN
Granted: June 14, 2018
Application Number:
20180164915
The sensing circuit includes including first input of a first electrode, a first set of inputs of a first set of two or more electrodes forming a first intersection and a second intersection, and a second set of inputs of a second set of two or more electrodes forming the second intersection and a third intersection. The sensing circuit includes a scan control circuit, coupled to the touch panel of electrodes, to concurrently select the sets of electrodes via a multiplexer. The touch…
Multi-Phase Self-Capacitance Scanning of Sensors Arrays
Granted: June 14, 2018
Application Number:
20180164914
Techniques for multi-phase self-capacitance (MPSC) scanning of a sensor array are described herein. In an example embodiment, a device comprises a sensor logic coupled to a processing logic. The sensor logic is configured to concurrently sense multiple sensor elements of the sensor array in each of multiple scanning operations in order to obtain multiple measurements, where each measurement represents a collective charge of the multiple sensor elements accumulated during a corresponding…
DETECT AND DIFFERENTIATE TOUCHES FROM DIFFERENT SIZE CONDUCTIVE OBJECTS ON A CAPACITIVE BUTTON
Granted: June 14, 2018
Application Number:
20180164359
Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the…
MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE
Granted: June 7, 2018
Application Number:
20180158919
Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer…
ENCRYPTION FOR XIP AND MMIO EXTERNAL MEMORIES
Granted: May 17, 2018
Application Number:
20180137294
Techniques for multiplexing between an execute-in-place (XIP) mode and a memory-mapped input/output (MMIO) mode for access to external memory devices are described herein. In an example embodiment, an IC device comprises a serial interface and a controller that is configured to communicate with external memory devices over the serial interface. The controller comprises a control register and a cryptography block. The control register is configured to indicate an XIP mode or a MMIO mode.…
Microcontroller Energy Profiler
Granted: May 17, 2018
Application Number:
20180136706
A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of…
FAST RAMP LOW SUPPLY CHARGE PUMP CIRCUITS
Granted: April 12, 2018
Application Number:
20180102704
Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage…
Stochastic signal density modulation for optical transducer control
Granted: April 5, 2018
Application Number:
20180098397
A controller for optical transducers uses stochastic signal density modulation to reduce electromagnetic interference.
MUTUAL CAPACITANCE SENSING ARRAY
Granted: April 5, 2018
Application Number:
20180095558
A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. Each sensor element comprises an outer frame including a conductive material. A cavity is formed within the interior of the outer frame.
Low-Power Type-C Receiver with High Idle Noise and DC-Level Rejection
Granted: April 5, 2018
Application Number:
20180095511
Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current…
TECHNIQUES FOR GENERATING MICROCONTROLLER CONFIGURATION INFORMATION
Granted: March 29, 2018
Application Number:
20180088912
An example includes accessing multiple configurations stored in a memory, where each configuration is associated with a corresponding circuit function implementable by an electronic device and associated with a corresponding set of resources of the electronic device. The example includes determining that one or more sets of resources of the electronic device are available for use by one or more configurations of the multiple configurations. Based on the determination, an embodiment…
Force Sensing
Granted: March 22, 2018
Application Number:
20180081479
An apparatus including a first signal generator of a force sensing circuit to output a first excitation (TX) signal on a first terminal and a second TX signal on a second terminal. The first terminal and the second terminal are configured to couple to a first force sensor and a reference sensor. The apparatus includes a first receiver channel coupled to a third terminal and a fourth terminal. The third terminal is configured to couple to the first force sensor and the fourth terminal is…
MEMORY SUBSYSTEM WITH WRAPPED-TO-CONTINUOUS READ
Granted: March 22, 2018
Application Number:
20180081564
Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second…
