Row redundancy with distributed sectors
Granted: November 27, 2018
Patent Number:
10141065
A semiconductor device comprises an embedded flash memory with row redundancy. The embedded flash memory comprises a memory bank that includes multiple physical sectors, where each physical sector comprises a plurality of erase sectors. In the memory bank, multiple portions of an additional erase sector are respectively distributed among the multiple physical sectors. The multiple portions of the additional erase sector are configured as a row-redundancy sector for the memory bank.
Technique for increasing the sensitivity of capacitive sense arrays
Granted: November 20, 2018
Patent Number:
10133432
A technique for operating a capacitive sensor array is described. The technique includes measuring a first capacitance of a first set of electrodes at a first time, measuring a second capacitance of a second set of electrodes at a second time, and calculating a position of a conductive object based on a relative magnitude of the first capacitance and the second capacitance. The first set and the second set includes at least one electrode in common and at least one electrode that is not…
Oxide formation in a plasma process
Granted: November 13, 2018
Patent Number:
10128258
A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the…
Method for providing read data flow control or error reporting using a read data strobe
Granted: November 6, 2018
Patent Number:
10120590
Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture.…
Low power capacitive sensor button
Granted: October 30, 2018
Patent Number:
10116307
Disclosed herein are system, methods, and apparatus for low power capacitive sensors. Apparatus may include a timing block configured to generate a repetitive trigger signal having a first frequency, and further configured to generate a clock signal having a second frequency. Apparatus may also include a sensing block coupled with the timing block and configured to, in response to the repetitive trigger signal, detect a change in capacitance associated with an object proximate to a…
Drain extended MOS transistors with split channel
Granted: October 16, 2018
Patent Number:
10103244
A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited…
System level interconnect with programmable switching
Granted: October 9, 2018
Patent Number:
10097185
In an example embodiment, a digital block comprises a datapath circuit, one or more programmable logic devices (PLDs), and one or more control registers. The datapath circuit comprises structural arithmetic elements. The one or more PLDs comprise uncommitted programmable logic. The one or more control circuits comprise a control register configured to store user-defined control bits, where the one or more control circuits are configured to control both the structural arithmetic elements…
Fast ramp low supply charge pump circuits
Granted: October 9, 2018
Patent Number:
10097086
Techniques for fast ramp, low supply charge-pump circuits are described herein. In an example embodiment, a non-volatile memory device comprises a flash memory array coupled to a fast charge-pump circuit. The charge-pump circuit comprises a first charge pump, an active charge pump coupled as input to the first charge pump, and a power supply coupled as input to the active charge pump. The active charge pump is configured to initialize the first charge pump to a greater absolute voltage…
Radical oxidation process for fabricating a nonvolatile charge trap memory device
Granted: October 2, 2018
Patent Number:
10090416
A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the…
Stable modulation index calibration and dynamic control
Granted: September 18, 2018
Patent Number:
10079699
Calibrating a Gaussian frequency-shift keying modulation index includes generating a training sequence of bits, shaping a pulse from the training sequence according to an initial modulation index, and converting the shaped signal to a transmission signal. The transmission signal is then either looped through a radio frequency core or processed by frequency deviation estimation hardware to determine a frequency deviation. The frequency deviation is converted to a new modulation index, and…
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
Granted: September 18, 2018
Patent Number:
10079314
A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
Method of integrating a charge-trapping gate stack into a CMOS flow
Granted: September 18, 2018
Patent Number:
10079243
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap…
Ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier
Granted: September 18, 2018
Patent Number:
10079240
Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric…
Methods and devices for reducing program disturb in non-volatile memory cell arrays
Granted: September 11, 2018
Patent Number:
10074438
A memory device that includes a pair of non-volatile memory cells, a first memory cell including a first memory gate and a first select gate, and a second memory cell including a second memory gate and a second select gate. The first and second memory cells share a source line, and the first and second memory gates are not connected to one another.
2T1C ferro-electric random access memory cell
Granted: September 11, 2018
Patent Number:
10074422
A memory device and method of operating the same are disclosed. Generally, the device includes an array of Ferro-electric Random Access Memory cells. Each cell includes a first transistor coupled between a bit-line and a storage node (SN) and controlled by a first wordline (WL1), a second transistor coupled between a reference line and the SN and controlled by a second wordline (WL2), and a ferro-capacitor coupled between the SN and a plateline. The device further includes a…
Touch sensor pattern
Granted: September 11, 2018
Patent Number:
10073563
An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device. The host includes decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance of one or more capacitors sensed…
Method of reducing charge loss in non-volatile memories
Granted: September 4, 2018
Patent Number:
10068912
A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the…
Baseline compensation for capacitive sensing
Granted: September 4, 2018
Patent Number:
10068121
A capacitance sensing circuit may include a charge to digital converter, coupled to a signal receiver channel, to receive a signal from a capacitive sense array. The capacitance sensing circuit may also include a baseline compensation signal generator, coupled to the signal receiver channel, to provide a baseline compensation signal in an opposite phase of the signal to the signal receiver channel.
Sensor-compatible overlay
Granted: August 28, 2018
Patent Number:
10061961
A sensor-compatible overlay is disclosed which uses anisotropic conductive material to increase capacitive coupling of a conductive object through the overlay material to a capacitive sensor. The anisotropic conductive material has increased conductivity in a direction orthogonal to the capacitive sensor. In one embodiment, the overlay is configured to enclose a device which includes a capacitive sensor. In another embodiment, the overlay is configured as a glove.
Embedded SONOS with triple gate oxide and manufacturing method of the same
Granted: August 28, 2018
Patent Number:
10062573
A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third…
