Low standby power with fast turn on for non-volatile memory devices
Granted: August 28, 2018
Patent Number:
10062423
Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
Sensor-compatible overlay
Granted: August 28, 2018
Patent Number:
10061961
A sensor-compatible overlay is disclosed which uses anisotropic conductive material to increase capacitive coupling of a conductive object through the overlay material to a capacitive sensor. The anisotropic conductive material has increased conductivity in a direction orthogonal to the capacitive sensor. In one embodiment, the overlay is configured to enclose a device which includes a capacitive sensor. In another embodiment, the overlay is configured as a glove.
Methods and devices for reading data from non-volatile memory cells
Granted: August 7, 2018
Patent Number:
10043555
Disclosed is a method for responding to a single user read command of a complementary cell array including one or more complementary cell pairs, the method including: determining if a first group of cells out of a data word is in an erased state or in a programmed state, and outputting a data word so that (a) if the first group of cells is determined to be erased a logical “one” is output for each bit of the data word and (b) if the first group of cells is determined to be programmed…
Advanced packet-based sample audio concealment
Granted: August 7, 2018
Patent Number:
10043523
In a reliable multi-cast, a concealment scheme may be applied to recover or conceal lost or otherwise corrupted packets of audio information for one channel based on the audio information of other channels in the reliable multi-cast.
NAND memory cell string having a stacked select gate structure and process for for forming same
Granted: July 31, 2018
Patent Number:
10038004
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the…
Integrated circuit device with reconfigurable digital filter circuits
Granted: July 24, 2018
Patent Number:
10033403
An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.
Memory architecture having two independently controlled voltage pumps
Granted: July 24, 2018
Patent Number:
10032517
A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is…
Capacitive field sensor with sigma-delta modulator
Granted: July 17, 2018
Patent Number:
10025441
A capacitive sensor includes a switching capacitor circuit, a comparator, and a charge dissipation circuit. The switching capacitor circuit reciprocally couples a sensing capacitor in series with a modulation capacitor during a first switching phase and discharges the sensing capacitor during a second switching phase. The comparator is coupled to compare a voltage potential on the modulation capacitor to a reference and to generate a modulation signal in response. The charge dissipation…
Memory device with multi-layer channel and charge trapping layer
Granted: July 10, 2018
Patent Number:
10020317
A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one…
PSoC architecture
Granted: July 10, 2018
Patent Number:
10020810
An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.
Split-gate semiconductor device with L-shaped gate
Granted: July 10, 2018
Patent Number:
10020316
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may…
Asymmetric pass field-effect transistor for nonvolatile memory
Granted: July 10, 2018
Patent Number:
10020060
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…
Systems, methods, and devices for parallel read and write operations
Granted: July 10, 2018
Patent Number:
10020034
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to…
Booting an application from multiple memories
Granted: July 10, 2018
Patent Number:
10019351
Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application.
Memory first process flow and device
Granted: July 3, 2018
Patent Number:
10014380
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure.…
Multiphase fingerprint sensor layout and construction
Granted: July 3, 2018
Patent Number:
10013593
A capacitive fingerprint sensor includes a set of capacitive sensor electrodes in a sensing area. The set of capacitive sensor electrodes includes a set of transmit (Tx) sensor electrodes, a set of receive (Rx) sensor electrodes, and a set of compensation electrodes. The fingerprint sensor also includes a multiphase capacitance sensor that is configured to perform a sensing scan of the capacitive sensor electrodes by applying a first Tx signal to a first subset of the Tx sensor…
Microcontroller programmable system on a chip
Granted: June 26, 2018
Patent Number:
10007636
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design…
Complementary SONOS integration into CMOS flow
Granted: June 19, 2018
Patent Number:
10002878
Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are…
10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
Granted: June 12, 2018
Patent Number:
9997237
A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and…
Complimentary SONOS integration into CMOS flow
Granted: June 12, 2018
Patent Number:
9997528
Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region…
