Complimentary SONOS integration into CMOS flow
Granted: June 12, 2018
Patent Number:
9997528
Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region…
Non-volatile memory array with memory gate line and source line scrambling
Granted: June 12, 2018
Patent Number:
9997253
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with…
10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof
Granted: June 12, 2018
Patent Number:
9997237
A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and…
Methods, circuits, devices and systems for sensing an NVM cell
Granted: June 5, 2018
Patent Number:
9991001
Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell.
Overlaid erase block mapping
Granted: June 5, 2018
Patent Number:
9990278
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB.…
Estimating angle measurements for source tracking using a phased array system
Granted: June 5, 2018
Patent Number:
9989633
Source tracking for phased array systems is described herein. One processing device includes a transceiver to transmit or receive radio frequency (RF) signals via a plurality of antenna elements and a processor coupled to the transceiver. The processor executes a multi-angle source-tracking tool configured to determine and store a set of angle estimation values of an angle between the plurality of antenna elements and the second antenna, a set of confidence measurements, and at least one…
Quasi-differential mutual capacitance measurement
Granted: May 29, 2018
Patent Number:
9983246
A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. The time required to bring the discharged integration capacitor to the same potential as the charged integration capacitor with a current source is measured as a single-slope analog-to-digital converter (ADC). The output of the ADC is representative of the…
Capacitance to code converter with sigma-delta modulator
Granted: May 22, 2018
Patent Number:
9977551
Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a…
Security system with a wireless security device
Granted: May 15, 2018
Patent Number:
9972146
A device includes a security controller to determine whether a wireless security device is authorized to access at least one resource protected by a secure access device based, at least in part, on identification signals that originate from the wireless security device. The security controller is configured to receive location information corresponding to the wireless security device from at least one wireless device. When the wireless security device is authorized to access at least one…
Configurable capacitor arrays and switched capacitor circuits
Granted: May 15, 2018
Patent Number:
9973200
Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.
Asynchronous transceiver for on-vehicle electronic device
Granted: May 15, 2018
Patent Number:
9971731
An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.
Charge trapping split gate device and method of fabricating same
Granted: May 8, 2018
Patent Number:
9966477
Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device.
Memory devices having embedded hardware acceleration and corresponding methods
Granted: May 8, 2018
Patent Number:
9965387
A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate…
Integrated circuit device with programmable analog subsystem
Granted: May 1, 2018
Patent Number:
9960773
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.
Control apparatus, switching power supply and control method for maintaining power conversion efficiency
Granted: May 1, 2018
Patent Number:
9960680
Disclosed herein are an apparatus for controlling a switch-mode power supply, and a method of operating the same. In an embodiment, it is determined whether or not a current of an inductor of the switching power supply has become less than or equal to a predetermined value. In an embodiment, a variable reference voltage is adjusted based on the current of the inductor and an output voltage. In an embodiment, a switch is turned off based on the inductor current, the output voltage, and…
PSoC architecture
Granted: April 24, 2018
Patent Number:
9954528
An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal.
Combined analog architecture and functionality in a mixed-signal array
Granted: April 24, 2018
Patent Number:
9952282
A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
Programmable switched capacitor block
Granted: April 17, 2018
Patent Number:
9948286
A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first…
Security network controller
Granted: April 10, 2018
Patent Number:
9942207
Described herein is a security network controller having a main bus to which is coupled a central processing unit, a cryptographic processing circuit, a security control circuit, and a memory controller. The security control circuit is configured to receive data stored in memory from the memory controller over the main bus and send the data over a first dedicated bus to the cryptographic processing circuit to obtain encrypted data. The security control circuit is further configured to…
Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices
Granted: March 27, 2018
Patent Number:
9928919
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for…
