Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices
Granted: March 27, 2018
Patent Number:
9928919
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for…
Capacitance sensing circuits, methods and systems having ground insertion electrodes
Granted: March 27, 2018
Patent Number:
9927926
A capacitance sensing system can include a plurality of transmit (TX) electrodes disposed in a first direction; a plurality of first electrodes disposed in a second direction and coupled to the TX electrodes by a mutual capacitance, and coupled to a capacitance sense circuit when at least one TX electrode receives a transmit signal; and a plurality of second electrodes structures, interspersed with the first electrodes and coupled to a ground node at least while the one TX electrode…
Optical navigation systems and methods for background light detection and avoiding false detection and auto-movement
Granted: March 27, 2018
Patent Number:
9927915
A method of operating an optical navigation system which includes disabling a light source to measure the ambient or external light level, comparing the measurement to a threshold level to determine whether the ambient light would cause false detection and light induced motion, and adjusting sensing parameter(s) to mitigate the effect of the ambient light.
Delta modulator receive channel for capacitance measurement circuits
Granted: March 20, 2018
Patent Number:
9923572
A circuit, system, and method for measuring capacitance are described. A current may be received at an input of a conversion circuit. The current may be converted to a voltage signal which may be used to create a negative feedback current to the input of the conversion circuit and which may be demodulated digitally to provide a static digital output representative of a capacitance.
Embedded SONOS based memory cells
Granted: March 20, 2018
Patent Number:
9922988
Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first…
Charge trapping split gate embedded flash memory and associated methods
Granted: March 20, 2018
Patent Number:
9922833
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor…
Flash memory cells having trenched storage elements
Granted: March 13, 2018
Patent Number:
9917211
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the…
Memory first process flow and device
Granted: March 13, 2018
Patent Number:
9917166
A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate…
Integration of a memory transistor into high-k, metal gate CMOS process flow
Granted: March 6, 2018
Patent Number:
9911746
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of…
Integration of a memory transistor into high-k, metal gate CMOS process flow
Granted: March 6, 2018
Patent Number:
9911747
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric…
Method of fabricating a charge-trapping gate stack using a CMOS process flow
Granted: March 6, 2018
Patent Number:
9911613
A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and…
Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch
Granted: March 6, 2018
Patent Number:
9910823
A stack processor using a non-volatile, ferroelectric random access memory (F-RAM) for both code and data space. The stack processor is operative in response to as many as 64 possible instructions based upon a 16 bit word. Each of the instructions in the 16 bit word comprises 3 five bit instructions and a 16th bit which is applicable to each of the 3 five bit instructions thereby making each instruction effectively 6 bits wide.
Restoring ECC syndrome in non-volatile memory devices
Granted: March 6, 2018
Patent Number:
9910729
A method of restoring an ECC syndrome in a non-volatile memory device having memory cells arranged in a plurality of sectors within a memory cell array, the method comprising identifying a first sector including at least one page having a disabled ECC (error correction code) flag; reading the value of all data bits in said at least one page; calculating values for ECC bits in said at least one page; and writing said data bit values and said calculated ECC bit values to a second sector in…
Uniformity correction method for low cost and non-rectangular touch sensor matrices
Granted: March 6, 2018
Patent Number:
9910544
A correction matrix for use with non-rectangular touch arrays is described. In one embodiment, a sensing device may include a memory and a processing element coupled to the memory. The memory may store a set of touch sense values corresponding to a measured characteristic of at least one unit cell of plurality of unit cells of a non-rectangular touch array and may store a correction matrix. The correction matrix may define an active region and an inactive region of the non-rectangular…
Detect and differentiate touches from different size conductive objects on a capacitive button
Granted: March 6, 2018
Patent Number:
9910077
Apparatuses and methods of distinguishing between a finger and stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the…
Frequency estimation, correction and noise suppression for modems
Granted: February 27, 2018
Patent Number:
9906386
A frequency-shift keying (FSK) demodulator includes a digital phase-locked loop (DPLL) based frequency estimator to convert a phase signal to a frequency signal, a frequency offset estimator to estimate and track direct current (DC) component of the frequency signal, and an average filter communicatively coupled to the frequency offset estimator to perform an accumulate-and-dump operation to improve a symbol-level signal to noise ratio (SNR) of the frequency signal.
Adjustable over-current detector circuit for universal serial bus (USB) devices
Granted: February 20, 2018
Patent Number:
9899825
A current detector circuit includes a current sense amplifier, coupled to a sense resistor, to receive a pair of input voltages and to output a first indicator signal responsive to a sensed input voltage difference produced by a sensed current passing through the sense resistor. The current detector circuit includes a comparator coupled to the current sense amplifier, the comparator to compare the first indicator signal to a reference voltage signal and output an interrupt signal…
Memory transistor with multiple charge storing layers and a high work function gate electrode
Granted: February 20, 2018
Patent Number:
9899486
An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric…
Memory architecture having two independently controlled voltage pumps
Granted: February 20, 2018
Patent Number:
9899089
A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is…
Power supply including regulating transistor for providing current to a load and non-volatile memory devices produced accordingly
Granted: February 13, 2018
Patent Number:
9892763
Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating…
