Systems, methods, and apparatus for memory cells with common source lines
Granted: April 18, 2017
Patent Number:
9627073
Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to…
Systems, methods, and devices for parallel read and write operations
Granted: April 18, 2017
Patent Number:
9627016
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to…
Type-C connector subsystem
Granted: April 18, 2017
Patent Number:
9625988
A Universal Serial Bus (USB) Type-C connector subsystem is described herein. An integrated circuit (IC) chip device includes a Universal Serial Bus (USB) Type-C subsystem. The USB Type-C subsystem is to operate an Ra termination circuit that consumes no more than a first predetermined amount of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, or to operate a standby reference circuit in a low power mode of the device to perform detection on a…
Hydrogen barriers in a copper interconnect process
Granted: April 18, 2017
Patent Number:
9624094
A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen;…
Embedded SONOS based memory cells
Granted: April 11, 2017
Patent Number:
9620516
Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first…
Split voltage non-volatile latch cell
Granted: April 11, 2017
Patent Number:
9620225
A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline…
Authentication for recognition systems
Granted: April 11, 2017
Patent Number:
9619645
Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.
Dynamically reconfigurable analog routing circuits and methods for system on a chip
Granted: April 4, 2017
Patent Number:
9612987
An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined…
Protecting circuit and integrated circuit
Granted: April 4, 2017
Patent Number:
9614366
Described herein are a protecting circuit and an integrated circuit capable of discharging electric current sufficient for an input voltage having a large time variation while suppressing power consumption. The protecting circuit includes: a first shunt circuit including a first shunt pathway connected to an input terminal, the first shunt circuit being configured to have a relatively low discharge capacity of the first shunt pathway and a relatively long response time; a second shunt…
Charge-trap NOR with silicon-rich nitride as a charge trap layer
Granted: April 4, 2017
Patent Number:
9614105
A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.
Methods and apparatus to detect a conductive object
Granted: April 4, 2017
Patent Number:
9612265
A method and apparatus scan a first capacitive sensor element that is located in a first scan region for a presence of a conductive object and then scan a second capacitive sensor element that is located in a second scan region for the presence of the conductive object. The scan of the first capacitive sensor element includes applying a ground voltage to a ground element through the second capacitive sensor element, the ground element located in the first scan region.
Negative high voltage hot switching circuit
Granted: March 28, 2017
Patent Number:
9608615
A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain…
Multi-bit non-volatile random-access memory cells
Granted: March 28, 2017
Patent Number:
9607695
Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may…
System-on-chip verification
Granted: March 21, 2017
Patent Number:
9600384
Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the…
Enhanced hydrogen barrier encapsulation method for the control of hydrogen induced degradation of ferroelectric capacitors in an F-RAM process
Granted: March 14, 2017
Patent Number:
9595576
An encapsulated ferroelectric capacitor or ferroelectric memory cell includes encapsulation materials adjacent to a ferroelectric capacitor, a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and an FEO encapsulation layer over the ferroelectric oxide to provide protection from hydrogen induced degradation.
High speed, high voltage tolerant circuits in flash path
Granted: March 14, 2017
Patent Number:
9595332
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.
Uniform signals from non-uniform patterns of electrodes
Granted: March 14, 2017
Patent Number:
9594462
Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern…
Interrupt latency reduction
Granted: March 7, 2017
Patent Number:
9588916
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
Multi-standard compliant USB battery charging scheme with detection of host disconnection in ACA-DOCK mode
Granted: March 7, 2017
Patent Number:
9590441
Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant…
Asymmetric pass field-effect transistor for non-volatile memory
Granted: March 7, 2017
Patent Number:
9589652
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…
