Use disposable gate cap to form transistors, and split gate charge trapping memory cells
Granted: March 7, 2017
Patent Number:
9590079
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a…
Split-gate semiconductor device with L-shaped gate
Granted: March 7, 2017
Patent Number:
9589805
A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may…
Asymmetric pass field-effect transistor for non-volatile memory
Granted: March 7, 2017
Patent Number:
9589652
A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a…
Interrupt latency reduction
Granted: March 7, 2017
Patent Number:
9588916
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
Granted: March 7, 2017
Patent Number:
9588881
A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of…
Memory access bases on erase cycle time
Granted: March 7, 2017
Patent Number:
9588695
Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
Capacitive sensing button on chip
Granted: March 7, 2017
Patent Number:
9588626
A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. The receive signal represents a mutual capacitance of the…
Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a gate oxide in a metal oxide semiconductor (MOS)
Granted: February 28, 2017
Patent Number:
9583501
A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a…
Analog-digital converter and control method
Granted: February 21, 2017
Patent Number:
9577654
In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of…
Control circuit
Granted: February 21, 2017
Patent Number:
9578699
Provided is a control circuit capable of suppressing flickering of an LED while preventing degradation of the power efficiency. A control circuit is configured to control electric power to an LED illumination based on a rectified drive voltage, the rectified drive voltage being a drive signal rectified by a rectifier, the drive signal being an AC signal whose phase is controlled by a dimmer including a switching device. The control circuit includes a time period detection part configured…
Memory devices and methods having multiple address accesses in same cycle
Granted: February 21, 2017
Patent Number:
9576630
A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.
Development, programming, and debugging environment
Granted: February 21, 2017
Patent Number:
9575748
A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program…
Reducing sleep current in a capacitance sensing system
Granted: February 21, 2017
Patent Number:
9575606
An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.
Gate fringing effect based channel formation for semiconductor device
Granted: February 14, 2017
Patent Number:
9570458
Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the…
High reliability non-volatile static random access memory devices, methods and systems
Granted: February 14, 2017
Patent Number:
9570152
A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to…
Dynamically configurable and re-configurable data path
Granted: February 7, 2017
Patent Number:
9564902
An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.
Apparatus and method for rounded ONO formation in a flash memory device
Granted: February 7, 2017
Patent Number:
9564331
A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of…
Body position sensing for equipment
Granted: February 7, 2017
Patent Number:
9564062
A device that includes a receiving surface for positioning at least one human body part, multiple capacitive sensor elements disposed within multiple positioning areas on the receiving surface, a sense circuit configured to compare the capacitance measurements of the sensor elements with threshold capacitance values and generate a signal when the capacitance measurements indicate proximity of a human body part on a positioning area, and an indicator configured to generate a notification…
SONOS type stacks for nonvolatile charge trap memory devices and methods to form the same
Granted: January 24, 2017
Patent Number:
9553175
A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.
System level interconnect with programmable switching
Granted: January 24, 2017
Patent Number:
9553588
Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional…
