Switching circuit
Granted: January 17, 2017
Patent Number:
9548729
A switching circuit includes a driver circuit DRV2 that outputs voltage for turning on and off a first transistor switch M2, positioned at a low potential side with respect to a load, among a plurality of transistor switches disposed in series between an input voltage and a ground; and a control circuit that causes the driver circuit DRV2 to output a first voltage that turns the first transistor switch M2 on upon an output voltage of the driver circuit DRV2 rising while the first…
Methods of fabricating an F-RAM
Granted: January 17, 2017
Patent Number:
9548348
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS…
Fingerprint sensor-compatible overlay
Granted: January 17, 2017
Patent Number:
9547788
A fingerprint sensor-compatible overlay which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. In one embodiment, the overlay is configured to…
Self aligned bump passivation
Granted: January 10, 2017
Patent Number:
9543262
A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.
End-of-life reliability for non-volatile memory cells
Granted: January 10, 2017
Patent Number:
9543017
A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.
Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning
Granted: January 10, 2017
Patent Number:
9542588
A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one…
Asynchronous transceiver for on-vehicle electronic device
Granted: January 10, 2017
Patent Number:
9541990
An on-vehicle electronic device has a generating unit configured to generate a first clock for data communication with another on-vehicle electronic device through a CXPI communication network; and an adjusting unit configured to adjust a duty width of the first clock.
Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same
Granted: January 3, 2017
Patent Number:
9537511
Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error.
Combining of results from multiple decoders
Granted: December 27, 2016
Patent Number:
9530103
Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number…
Fractured erase system and method
Granted: December 20, 2016
Patent Number:
9524247
Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein…
Control circuit of step-down DC-DC converter, control circuit of step-up DC-DC converter and step-up/step-down DC-DC converter
Granted: December 20, 2016
Patent Number:
9523990
A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit 11 of a current mode step-down DC-DC converter 1 includes a slope compensation circuit SC and an offset circuit IF1. The slope compensation circuit SC adds an increase gradient m2 due to slope compensation to an increase gradient of a coil current waveform Vsense in a range wherein an ON period Ton of a switch SW1 exceeds ½ of an operating cycle T. An offset circuit IF1 applies an…
Method and system for processing a semiconductor wafer using data associated with previously processed wafers
Granted: December 20, 2016
Patent Number:
9523976
A method of processing a wafer in a production tool includes receiving a wafer at a process tool, the wafer associated with a wafer process history, acquiring data associated with wafers processed by the process tool and having the wafer process history, when the amount of acquired data is insufficient, acquiring additional data associated with wafers processed by the process tool and having a process history differing from the wafer process history by a single factor, when the amount of…
Integrated circuit device with on-board calibration of signal generator circuits, and related methods
Granted: December 13, 2016
Patent Number:
9520888
An integrated circuit (IC) device can include at least one phase or delay lock loop (P/DLL) circuit comprising a plurality of circuit sections, at least one of the circuit sections responsive to digital calibration values to alter at least one periodic output signal; a nonvolatile memory (NVM) circuit formed in the same IC package as the at least one P/DLL circuit and configured to store the calibration values; and a processing circuit formed in the same IC package as the at least one…
Systems, methods, and devices for energy and power metering
Granted: December 6, 2016
Patent Number:
9513319
Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated…
Programmable input/output circuit
Granted: December 6, 2016
Patent Number:
9515659
A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.
Non-volatile static RAM and method of operation thereof
Granted: December 6, 2016
Patent Number:
9514816
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.
Hybrid reference generation for ferroelectric random access memory
Granted: December 6, 2016
Patent Number:
9514797
An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in…
Phoneme score accelerator
Granted: December 6, 2016
Patent Number:
9514739
Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs…
Debug control circuit
Granted: December 6, 2016
Patent Number:
9514070
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command…
Input/output multiplexer bus
Granted: December 6, 2016
Patent Number:
9513322
One embodiment includes an I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.
