Hybrid reference generation for ferroelectric random access memory
Granted: December 6, 2016
Patent Number:
9514797
An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in…
Phoneme score accelerator
Granted: December 6, 2016
Patent Number:
9514739
Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs…
Debug control circuit
Granted: December 6, 2016
Patent Number:
9514070
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for freeing a bus in a time period between a command transfer request and a command transfer operation. The method and apparatus set, with the control circuit, a second operation mode in which a split transaction is not issued and transfer, with the control circuit, the command to a processing unit via the bus in response to the command…
Input/output multiplexer bus
Granted: December 6, 2016
Patent Number:
9513322
One embodiment includes an I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.
Systems, methods, and devices for energy and power metering
Granted: December 6, 2016
Patent Number:
9513319
Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated…
Three-dimensional charge trapping NAND cell with discrete charge trapping film
Granted: November 29, 2016
Patent Number:
9508736
A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel…
Semiconductor device and method of manufacturing the same
Granted: November 29, 2016
Patent Number:
9508651
A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the…
Execution history tracing method
Granted: November 29, 2016
Patent Number:
9507688
An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as…
Technique for increasing the sensitivity of capacitive sensor arrays
Granted: November 29, 2016
Patent Number:
9507465
A technique for operating a capacitive sensor array. The technique includes logically grouping capacitance sensors of an array of capacitance sensors into sensor groups. The sensor groups each include at least two capacitance sensors of the array of capacitance sensors. Values indicative of a capacitance for each of the sensor groups are measured. The measured values are then analyzed to determine a location of a user interaction with the array of capacitance sensors.
Output switching circuit
Granted: November 22, 2016
Patent Number:
9502979
An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating…
Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate electrode
Granted: November 22, 2016
Patent Number:
9502543
Methods of fabricating a memory device are described. Generally, the method begins with forming a tunnel dielectric layer over a channel region formed from a silicon containing layer over a surface of a substrate. A first oxygen-rich nitride layer of a multi-layer charge-trapping region is formed on a surface of the tunnel dielectric layer, and a second oxygen-lean nitride layer formed over the first nitride layer. A blocking dielectric layer is formed over a surface of the second layer…
Methods and apparatus to detect a presence of a conductive object
Granted: November 22, 2016
Patent Number:
9501168
A method and apparatus determine a plurality of regions, each of the plurality of regions having a detected change in capacitance value that meets or exceeds a threshold value. In an embodiment, the method and apparatus fit a shape to the plurality of regions and determine another region, the other region being within the fitted shape and not having the detected change in capacitance value that meets or exceeds the threshold value. The method and apparatus may assign an assigned change…
Capacitance measurement system and methods
Granted: November 22, 2016
Patent Number:
9500686
A first capacitor and a second capacitor are charged until voltage at the second capacitor settles to a settling voltage. While charging, the first capacitor is alternately switched between a current source and ground. When the settling voltage is reached, charging of the first capacitor is halted. The second capacitor continues to be charged until voltage at the second capacitor reaches a reference voltage. The amount of time it takes for the settling voltage to reach the reference…
Method of fabricating a charge-trapping gate stack using a CMOS process flow
Granted: November 15, 2016
Patent Number:
9496144
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory…
Increasing lithographic depth of focus window using wafer topography
Granted: November 15, 2016
Patent Number:
9494853
Various embodiments provide for topography aware optical proximity correction that can improve depth of focus during wafer lithography. The system can determine the topography of the wafer using real process information. The topographical variations can be based on random defects or structural details. The system can divide the wafer into regions based on the topography of the regions and determine depth of focus values for each of the regions. Optical proximity correction can then be…
Distribution of gas over a semiconductor wafer in batch processing
Granted: November 15, 2016
Patent Number:
9493874
A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.
Multi-port integrated circuit devices and methods
Granted: November 8, 2016
Patent Number:
9489326
An integrated circuit device may include a first integrated circuit (IC) portion having a memory array that stores data units as storage locations and burst access circuitry that sequentially accesses N relates storage locations within the memory array, where N>1; and a second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access register having register locations to store at least N data units, and being coupled to a…
Capacitance sensing circuits, methods and systems having conductive touch surface
Granted: November 8, 2016
Patent Number:
9490804
A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes.
Minimizing disturbs in dense non volatile memory arrays
Granted: November 8, 2016
Patent Number:
9490261
A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at…
Resistive memory array using P-I-N diode select device and methods of fabrication thereof
Granted: November 8, 2016
Patent Number:
9490126
An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.
