Auto-detecting CMOS input circuit for single-voltage-supply CMOS
Granted: August 10, 2010
Patent Number:
7773357
An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input biasing transistors to ensure that no gate oxide exposed to external voltages sustains a voltage greater than a predefined value. Bias selectors select an available highest voltage to reverse bias corresponding floating wells and…
Combination offset voltage and bias current auto-zero circuit
Granted: July 20, 2010
Patent Number:
7760015
A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier.
Digital pulse-width modulator based on non-symmetric self-oscillating circuit
Granted: May 4, 2010
Patent Number:
7710174
A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also…
Digital pulse frequency/pulse amplitude (DPFM/DPAM) controller for low-power switching-power supplies
Granted: May 4, 2010
Patent Number:
7710209
A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.
Communications system with segmenting and framing of segments
Granted: April 20, 2010
Patent Number:
7701976
A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloads into a packet, a first interface configured to transmit the packet, and a second interface configured to transmit segment information about the segments in the packet.
Interrupt based multiplexed current limit circuit
Granted: April 13, 2010
Patent Number:
7696912
A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC…
Amplitude regulated crystal oscillator
Granted: March 30, 2010
Patent Number:
7688154
To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/drain voltage of a differential amplifier driving the crystal oscillator across its input terminals is reduced so as to lower the amplitude of the oscillation signal. If the detected peak level is determined as being smaller…
Open-drain output buffer for single-voltage-supply CMOS
Granted: March 23, 2010
Patent Number:
7683696
An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching…
Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters
Granted: February 23, 2010
Patent Number:
7667625
A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.
Programmable analog-to-digital converter for low-power DC-DC SMPS
Granted: January 26, 2010
Patent Number:
7652604
A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the…
Means to detect a missing pulse and reduce the associated PLL phase bump
Granted: January 12, 2010
Patent Number:
7646224
A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has a data input terminal responsive to a voltage supply, and a clock terminal responsive to an inverse of feedback clock. The second flip-flop has a data input terminal responsive to an output of the first flip-flop, and a clock…
Method and apparatus for terminating/generating physically and virtually concatenated signals
Granted: November 17, 2009
Patent Number:
7620030
A SONET signal is terminated by pointer processing a physically concatenated SONET signal to output a pointer processed physically concatenated SONET signal. Virtual concatenation-related byte markers (for example, H4 and J1) are then inserted into the pointer processed physically concatenated SONET signal. Virtual concatenation overhead data (for example, MFI and SEQ#) is then inserted into the pointer processed physically concatenated SONET signal so as to produce a converted virtually…
Methods of using predictive analog to digital converters
Granted: October 27, 2009
Patent Number:
7609185
Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is…
Smart talk backlighting system and method
Granted: September 15, 2009
Patent Number:
7589704
A smart talk mechanism provides feedback information from a driver to a DC-to-DC converter, enabling the DC-to-DC converter to adjust an input voltage for at least one illumination source backlighting the display for increasing the power efficiency.
Communications system with first and second scan tables
Granted: September 15, 2009
Patent Number:
7590130
A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identified by the first channel identification. The second stage is configured to receive the data and select a second channel identification from the second scan table to provide the received data at essentially a data rate of the…
Model predictive thermal management
Granted: August 11, 2009
Patent Number:
7574321
Electrical components which substantially dissipate the power provided them in the form of heat will change temperature in response to self heating, heat transfer to their surroundings, and heat transferred from one component to another. A method is disclosed for calculating the temperature of a component(s) using a thermal model. In one embodiment the power dissipation of each component is controlled to limit the temperature of the component. In one embodiment the temperature of a…
Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition
Granted: June 2, 2009
Patent Number:
7543163
A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly and supplies clock signals to the logic controller for quickly awakening the controller so the latter can to respond to exigent circumstances. One such circumstance can be the drop of a vital supply voltage below a predefined…
Method for charging a battery using a constant current adapted to provide a constant rate of change of open circuit battery voltage
Granted: May 5, 2009
Patent Number:
7528571
A method for charging a battery is disclosed, wherein a constant current charging current is periodically adjusted as needed such that the change in battery voltage increases approximately linearly during the charging period. In some embodiments the charging is in three phases. An optional first phase charges with a low current until the battery voltages rises to a certain minimum. During a second phase a constant current is provided while the battery voltage is monitored. The second…
Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS
Granted: April 28, 2009
Patent Number:
7525471
In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital…
Self-calibrating digital pulse-width modulator (DPWM)
Granted: December 2, 2008
Patent Number:
7459951
A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit.
