Fast loop laser diode driver
Granted: November 25, 2008
Patent Number:
7457335
A laser diode driver circuit can comprise fast loop portion and a closed-loop portion. The closed-loop driver portion can provide a part of the current for a laser diode. The closed-loop drive portion output can be independent of a photodetector. The fast-loop driver portion can provide a second part of the current for the laser diode. The fast-loop driver portion can use the output of the photodiode to determine the output of the fast-loop driver portion.
Method and apparatus for adapting mac and network processor core to packet format changes and for mapping RPR architecture over spatial reuse architecture
Granted: October 21, 2008
Patent Number:
7441039
A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantially protocol-independent core portion that is insulated from protocol changes. Translation and/or adaptation mechanisms in the peripheral portion of the device allow the device to handle changes in data format and/or pipeline…
Variable sub-bandgap reference voltage generator
Granted: October 14, 2008
Patent Number:
7436245
A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may be varied. To achieve this, a first voltage having a positive temperature coefficient is multiplied by a first ratio defined by first and second resistive values to generate a second voltage. A third voltage having a negative…
Phase detector for RZ
Granted: August 12, 2008
Patent Number:
7411426
A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in…
Elimination of dummy detector on optical detectors using input common mode feedback
Granted: August 12, 2008
Patent Number:
7411460
A voltage reference forces a constant voltage at the inputs to an amplifier, thereby negating a need for a dummy detector on the non-active input of the amplifier.
Predictive analog to digital converters and methods of using
Granted: July 29, 2008
Patent Number:
7405689
Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the…
Low power CMOS LVDS driver
Granted: February 12, 2008
Patent Number:
7330056
A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching stage. A control circuit provides the voltages that are applied to the voltage-controlled resistor and the voltage-controlled current sink. The voltage applied to the voltage-controlled resistor defines the high output voltage.…
Differential operational amplifier
Granted: January 1, 2008
Patent Number:
7315210
The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four primary input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate at least four intermediate signals that are delivered…
Memory-efficient conversion between differing data transport formats of SONET overhead data
Granted: November 6, 2007
Patent Number:
7292603
In a SONET apparatus, the data flow differences between OC-768 and OC-192 can be exploited to effectuate conversion between OC-768 and OC-192 using as little as 256 bytes of memory.
Dual data rate flip-flop
Granted: July 10, 2007
Patent Number:
7242235
A flip-flop is configured to operate either in a double data-rate mode or a normal mode. When configured to operate in the double data-rate mode, the flip-flop outputs data on both edges of the applied clock. When configured to operate in the normal mode, the flip-flop outputs data on either the rising or falling edges of the applied clock. In the double data-rate mode, when a first latch disposed in the flip-flop operates in a sampling mode, the second latch disposed in the flip-flop…
Microprocessor with customer code store
Granted: May 8, 2007
Patent Number:
7216220
A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level…
Method and apparatus to generate break before make signals for high speed TTL driver
Granted: April 3, 2007
Patent Number:
7199616
A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the…
Interleaved pulse-extended phase detector
Granted: October 24, 2006
Patent Number:
7127021
A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by…
Differential amplifier
Granted: September 26, 2006
Patent Number:
7113040
The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate four intermediate signals that are delivered to the output…
High speed differential resistive voltage digital-to-analog converter
Granted: September 19, 2006
Patent Number:
7109904
A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are…
Detection of a closed loop voltage
Granted: September 5, 2006
Patent Number:
7102393
To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter…
CMOS LvPECL driver with output level control
Granted: August 15, 2006
Patent Number:
7091754
A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the…
CMOS bandgap reference with low voltage operation
Granted: July 18, 2006
Patent Number:
7078958
A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to include a multitude of output stages. Each output stage may be…
Reverse-biased P/N wells isolating a CMOS inductor from the substrate
Granted: June 6, 2006
Patent Number:
7057241
A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the…
Pixel-by-pixel digital control of gain and offset correction for video imaging
Granted: May 2, 2006
Patent Number:
7038720
A method and apparatus for adjusting, on a pixel-by-pixel basis, the gain and offset in an AFE as the pixels are sequentially processed. Although the method can be used for any purpose, it is directed in particular to light source non-linearity, such as edge effects of a scanner. A unique clocking method clocks the gain and offset values into the register at a higher clock rate than the image sampling rate.
