CMOS analog switch with auto over-voltage turn-off
Granted: March 14, 2006
Patent Number:
7012794
An analog transfer gate that can be connected to an external line of a chip that is also connected to a digital circuit. The transfer gate includes both NMOS and PMOS transistors for passing the analog signals in both directions. A voltage sensing circuit is connected to the external line and is configured to sense a voltage that is higher than the supply voltage of the analog circuit. When this occurs, it produces a sense output signal. The sense output signal activates a protection…
Simplifying verification of an SFI converter by data format adjustment
Granted: February 14, 2006
Patent Number:
7000158
The present invention enables interface conversion verification with a single chip and improves problem isolation. Exemplary embodiments of the present invention can provide this by modifying the input data pattern (e.g., creating a 40G, or pseudo OC-768, frame by multiplexing four OC-192 frames, two bytes at a time) to provide per port demultiplexing of data streams at the output of the interface converter.
Method and apparatus for byte rotation
Granted: November 15, 2005
Patent Number:
6965606
A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, data alignment may involve the prediction of a rotation amount for unaligned data bytes. The rotation amount is predicted one clock cycle before actual rotation of data bytes based on the current contents of a buffer. The one cycle look ahead enables a large…
High speed phase selector
Granted: November 1, 2005
Patent Number:
6960942
Method and circuitry for selecting phases while avoiding glitches in the output signal during phase switching. An integrated circuit having a plurality of input terminals coupled to receive a respective plurality of clock signals having different phases, and a plurality of control terminals coupled to receive a respective plurality of phase selection signals. The circuit is configured to output a first selected clock signal from the plurality of clock signals in response to a first…
Image sampling circuit with a blank reference combined with the video input
Granted: October 4, 2005
Patent Number:
6952240
A programmable gain amplifier having three separately programmable amplifiers. A programmable transconductance amplifier is followed by a programmable transimpedance amplifier, then a programmable switched capacitor amplifier. In one embodiment, this programmable gain amplifier is implemented in an analog front-end (AFE) circuit. One AFE embodiment provides a coarse pre-gain offset a black reference level sampler, and a fine post-gain offset in the programmable switched capacitor…
UART with compressed user accessible interrupt codes
Granted: September 20, 2005
Patent Number:
6947999
An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the…
Frequency compensation of wide-band resistive gain amplifier
Granted: June 14, 2005
Patent Number:
6906593
A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to…
UART automatic half-duplex direction control with programmable delay
Granted: March 8, 2005
Patent Number:
6865626
A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.
Clock recovery circuit
Granted: September 28, 2004
Patent Number:
6798857
A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison…
Black level offset calibration system for CCD image digitizer
Granted: August 10, 2004
Patent Number:
6774942
An improved offset correction circuit for an image digitizing system having a correlated double sample and hold circuit, a programmable gain amplifier and an analog-to-digital converter. The output of the analog-to-digital converter is provided to a dual offset correction circuit. The dual offset correction circuit provides both first and second correction values as feedback signals. In one embodiment, the first correction value is a coarse correction which is applied prior to…
UART clock wake-up sequence
Granted: June 22, 2004
Patent Number:
6754839
A UART with a clock oscillator that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator is awakened, the counter counts up to a specified count. Upon reaching the specified count, the output of the counter is enabled, which is connected to an interrupt line for generating an interrupt. In one embodiment, the IC need not be a UART, and no interrupt code (or a default code of all zeros or other default) is provided for the interrupt,…
CMOS transmission gate with high impedance at power off
Granted: June 8, 2004
Patent Number:
6747503
A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the…
Loop filter capacitor multiplication in a charge pump circuit
Granted: June 1, 2004
Patent Number:
6744292
A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.
Short circuit power limiter
Granted: April 6, 2004
Patent Number:
6717783
The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power limiter then reduces the power consumption of the target circuit. In a specific example, the power limiter toggles a particular portion of the target circuit on and off to reduce the circuit's…
I/O pad overvoltage protection circuitry
Granted: March 2, 2004
Patent Number:
6700431
A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This…
Bounce tolerant fuse trimming circuit with controlled timing
Granted: February 17, 2004
Patent Number:
6693783
A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long…
Input termination with high impedance at power off
Granted: January 27, 2004
Patent Number:
6683473
An input termination circuit with high impedance at power off, which includes a first transistor coupled between a first terminal and a second terminal. The input termination circuit also includes a control circuit that monitors voltages on the first and second terminals and a first voltage source. During power off conditions, the control circuit couples the gate of the first transistor to a voltage that will keep the first transistor off. The first transistor remains off even when the…
Single-seed wide-swing current mirror
Granted: January 20, 2004
Patent Number:
6680605
A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two functions. First, the source current itself flows through the transistors of the transistor biasing circuit to the two transistors forming the first leg of the current mirror. Second, the transistor…
Wide-band replica output current sensing circuit
Granted: September 23, 2003
Patent Number:
6624671
An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output impedance. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect…
Power down circuit for high output impedance state of I/O driver
Granted: July 22, 2003
Patent Number:
6597222
A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby…
