Low power wide bandwidth programmable gain CDS amplifier/instrumentation amplifier
Granted: June 3, 2003
Patent Number:
6573784
A method and circuitry for implementing programmable gain. More particularly, embodiments of the present invention provide an amplifier circuit which can be used as a CDS-amp or an instrumentation amplifier. Included is a two-stage amplifier, each stage having a few as one transistor. A current source biases one stage of the two-stage amplifier. A load resistor network couples to the two-stage amplifier and is configured to set gain values for the two-stage amplifier.
Self-powered, maximum-conductive, low turn-on voltage CMOS rectifier
Granted: December 31, 2002
Patent Number:
6501320
A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier circuit, respectively. The invention provides a self-contained, self-powered, self-regulated low turn-on voltage diode-rectifier with maximum current (on-state conductance) when forward-biased. This…
Dynamic biasing techniques for low power pipeline analog to digital converters
Granted: October 8, 2002
Patent Number:
6462695
A method and circuitry for implementing low-power analog-to-digital converters. More particularly, embodiments of the present invention provide an amplifier circuit for pipeline ADCs having multiple stages, some in sample mode, some in hold mode. The stages include residue amplifiers which include a pre-amp and a current source. The current source is turned off during the sample mode. Some embodiments include a second current source that provides a bleeder current during the sample phase…
Low-powered, self-timed, one-time in-circuit programmable MOS fuse element and circuit
Granted: September 17, 2002
Patent Number:
6452248
A programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby programming the MOS transistor. A programming circuit with the MOS transistor in a feedback path is provided. This feedback provides a self-timing feature, such that immediately after the fuse is programmed, its…
Automatic frequency rate switch
Granted: September 17, 2002
Patent Number:
6452425
A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode,…
Rising and falling edge aperture delay control circuit in analog front end of imaging system
Granted: July 23, 2002
Patent Number:
6424197
A programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic then combines the outputs of the two delay circuits to produce an output clock with separately delayed rising and falling edges.
ESD structure for IC with over-voltage capability at pad in steady-state
Granted: July 23, 2002
Patent Number:
6424510
The present invention provides an ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the…
Control point generation and data packing for variable length image compression
Granted: June 11, 2002
Patent Number:
6404927
A simple, cost-effective compression circuit which compress raw color data without interpolation. Control points common to all the colors in a line are generated each time one of the colors exceeds the color change threshold. The change in the other color is recorded at the same time even though it doesn't exceed the minimum change threshold.
Slew-rate-control structure for high-frequency operation
Granted: March 19, 2002
Patent Number:
6359484
The present invention provides an integrated circuit driver having multiple resistance paths that switch on at different stages of the rising and falling transitions of the driver's output signal waveform. The driver also has a control circuit configured to turn on the one or more resistance paths during at least one predetermined stage of the output signal during transitions, thus reducing the control circuit's effective resistance to control the slope of the transitions…
Digital jitter attenuator using an accumulated count of phase differences
Granted: February 26, 2002
Patent Number:
6351165
A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is positive or negative. When the counter reaches a pre-specified up or down count, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used…
CMOS image sensor with high quantum efficiency
Granted: February 26, 2002
Patent Number:
6350979
An image sensor integrated circuit with a pixel cell having photogates wherein each photogate has a number of gaps which allow light to penetrate to the substrate. The gaps are open in the direction of the floating diffusion, in order to minimize the trapping of charges. In a preferred embodiment, the floating gate has a comb structure, with the tines of the comb extending toward the floating gate. Preferably, the tines or fingers are wider than the gaps. In a preferred embodiment, the…
Programmable power consumption pipeline analog-to-digital converter with variable resolution
Granted: January 22, 2002
Patent Number:
6340944
An analog-to-digital converter which has a low resolution and high resolution mode. In response to the low resolution mode signal, a switching circuit selects only certain of the digital bit outputs. In one embodiment, the analog-to-digital converter is a pipelined circuit with a number of stages. In response to the low resolution mode, a number of the stages are bypassed, so that only the needed stages for the smaller number of bits are used. The stages that are bypassed are preferably…
Second order digital jitter attenuator
Granted: December 25, 2001
Patent Number:
6333651
A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to an integration circuit. The phase detector also indicates whether the phase difference is positive or negative. The output of the integration circuit is provided to a comparator, which compares the value to a threshold. When the threshold is exceeded, an advance or retard signal is provided to a phase selector.…
High-frequency high-current line driver
Granted: December 4, 2001
Patent Number:
6326820
The present invention provides a compensation circuit having a first and a second compensation transistor. The compensation circuit is configured for tying a transconductance, gm, of a first and a second output transistor to a conductance, gds, of the the first and second compensation transistors, respectively, such that a gm-to-gds ratio becomes fixed. The tying stabilizes and prevents movement of the location of the compensation zero. The compensation zero is created by the…
Indirect output current sensing
Granted: November 27, 2001
Patent Number:
6323703
An indirect current sensing circuit and method for current limiting output driver circuitry is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and…
Low-power integrated circuit I/O buffer
Granted: November 6, 2001
Patent Number:
6313671
The present invention provides a buffer circuit that consumes little power. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V) at an interface node. In a preferred embodiment, the buffer circuit has a driver PMOS transistor, and a pre-driver circuit having a pull-up circuit coupled to the interface node via a PMOS switch transistor and a first PMOS pass transistor. The pre-driver…
Over-voltage tolerant integrated circuit I/O buffer
Granted: November 6, 2001
Patent Number:
6313672
The present invention provides a buffer circuit that can tolerate over-voltage, and a method for protecting buffer circuits from over-voltage. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V). In a preferred embodiment, the buffer circuit has a pre-driver circuit having a pull-up circuit coupled to an interface node via a PMOS switch transistor. The pre-driver biasing circuit is…
IC with dual function clock and device ID circuit
Granted: October 30, 2001
Patent Number:
6311246
An integrated circuit in which the address and data inputs for a clock register to program a clock is also used for device ID and revision number. A shadow register is provided which is accessible to output the ID and revision number when (1) the regular clock register is addressed, and (2) a particular data input for activating the shadow register appears on the data input to the clock register.
Voltage regulated charge pump
Granted: October 9, 2001
Patent Number:
6300820
A voltage regulated charge pump is disclosed which is capable of regulating its output voltage without radiating switching noise or consuming more power than is necessary to maintain the output at its targeted level. The voltage regulated charge pump circuit and its method of regulation, according to the present invention, can reliably drive transmission lines in networking system and communication applications.
Programmable highly temperature and supply independent oscillator
Granted: December 5, 2000
Patent Number:
6157270
An oscillator circuit generates an output frequency that is substantially independent of power supply and temperature variations. The oscillator circuit can be implemented using conventional complementary metal-oxide-semiconductor technology. The oscillator circuit is suitable for use as an internal oscillator for generating a stable reference frequency in telecommunication receiver modules.
