Post-conversion system for an analog-to-digital converter which sets an added bit of resolution if an intermediate sample is within a threshold
Granted: October 3, 2000
Patent Number:
6127956
Post processing of the converted digital bits from an ADC to provide one or more additional bits of resolution. The additional bits of resolution will be accurate for data which is locally correlated, such as image data. For a particular digital sample, a curve (such as a straight line) is fitted through adjacent samples to determine an expected value for the current sample. The actual digital sample is compared to the expected value to determine whether it is within a threshold of the…
Universal duty cycle adjustment circuit
Granted: September 19, 2000
Patent Number:
6121805
A duty cycle control circuit that consumes lower power and smaller silicon area, and is less susceptible to noise or jitter. In one embodiment, the invention includes a divide-by-two circuit that is edge triggered and generates a signal at its output with half the frequency of the input signal but with a 50% duty cycle. The divide-by-two circuit is followed by a frequency restore circuit that restores the original frequency of the input signal but with its duty cycle regulated at about…
Constant gain amplifier
Granted: September 19, 2000
Patent Number:
6121837
An operational amplifier that exhibits a relatively constant gain over process and temperature variations. The operational amplifier according to the present invention is designed such that its gain does not depend on process sensitive parameters such as mobility of field effect transistors.
Differential output driver with monotonic output transitions
Granted: August 29, 2000
Patent Number:
6111433
Method and circuitry for differential output driver with monotonic output transitions. The switching sequence for the output driver transistors of the differential driver changes depending on the direction of the input signal transition. When the input makes a binary transition from high to low, each one of the output driver transistors is switched on or off at a different time based on a first predetermined sequence. When the input makes the opposite binary transition (low to high),…
Low pressure sensor with a thin boss and method of manufacture
Granted: July 25, 2000
Patent Number:
6093579
A robust and highly sensitive pressure sensing device with good linearity made with a thin-bossed diaphragm, and a process to manufacture the same that involves minimal additional steps and is fully compatible with conventional bulk micromachining processes that are used to make standard pressure sensors.
Transmission line driver with high output impedance at power off
Granted: March 14, 2000
Patent Number:
6037828
Circuit techniques for allowing the sharing of the same output terminals between transmission line drivers that comply with differing protocols. By inserting isolation transistors at the outputs of line driver circuits, and in a preferred embodiment along the current loop of a current-output line driver circuit, the invention allows the sharing of output pins while meeting all the power on and power off requirements of different protocols.
Slew rate limited output driver
Granted: February 29, 2000
Patent Number:
6031389
A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic…
High-voltage switch control
Granted: September 28, 1999
Patent Number:
5959494
Method and circuitry for reliably controlling the state of a transistor switch under high voltage conditions are disclosed. The present invention monitors the level of an external signal applied to one terminal of the switch. If the level of the external signal is lower than a reference voltage such as the power supply voltage of the integrated circuit that comprises the switch, the control of the switch is passed to a digital signal internal to the integrated circuit. If the level of…
Multi-function FIFO counter status register
Granted: September 7, 1999
Patent Number:
5949787
A single, standard general purpose register address accesses not only the general purpose register, but, pursuant to user programming, FIFO counter status. In one embodiment, either the receive or transmit FIFO counter status can be accessed. The use of the general purpose register address for this purpose is preferably programmed using a bit from the control register on the chip.
Single pole current mode common-mode feedback circuit
Granted: August 3, 1999
Patent Number:
5933056
A CMFB circuit that contains only one voltage amplifier in the loop, and is therefore immune to multi-pole stability problems. This is accomplished by providing feedback in the form of current which sums with a constant node current of the differential voltage amplifier. This control current source is created with two transistors, one controlled by the desired, common-mode voltage level, and another connected to the actual, measured common-mode output level.
Out-of-range detector for pipeline ADC
Granted: July 27, 1999
Patent Number:
5929799
Out-of-range comparators for an analog-to-digital converter at other than the first stage of a pipeline ADC. By using a subsequent stage, the accuracy required for the ADC is reduced. The offset voltage of these comparators are reduced when input referred through the gain of the cascade of pipeline amplifiers in front of it, thus reducing the necessary accuracy required for out-of-range indication. This results in the accuracy requirement of the out-of-range comparators being greatly…
CMOS soft clipper
Granted: July 13, 1999
Patent Number:
5923203
A soft clipper circuit in CMOS technology not only allows the knee to be programmed, but also the slope of the curve after the knee to be programmed. This is accomplished by putting a second transconductance in parallel with the first transconductance, and using a switching circuit to connect the output of the second transconductance to that of the first transconductance when the knee level is reached. This is determined by a comparator which has an input coupled to the second…
Charge injection cancellation technique
Granted: July 13, 1999
Patent Number:
5923206
An MOS FET circuit with a summing circuit at the input of an amplifier to provide charge cancellation. The summing circuit is capacitively coupled to the input with a charge cancellation capacitor. A separate amplifier, having components substantially the same as the components of the first amplifier, is connected through the charge cancellation capacitor to the first amplifier.
Isolation circuit for I/O terminal
Granted: June 22, 1999
Patent Number:
5914627
Circuits and method for isolating internal nodes of an integrated circuit from external signals applied to I/O terminals of the IC even under no-power conditions are disclosed. The invention senses the most positive voltage level (in case of a p-channel implementation) or the most negative voltage level (in case of an n-channel implementation) at two input or input/output (I/O) pads and uses that voltage to isolate the internal nodes of the integrated circuit from the pad, without…
Negative charge pump circuit
Granted: June 22, 1999
Patent Number:
5914632
A charge pump circuit that is capable of generating a voltage that is greater in absolute magnitude than that of the substrate voltage Vsub in circuits where the substrate cannot be pumped to a voltage that is greater in absolute magnitude than Vsub is disclosed. Various innovative circuit techniques are used to implement a, for example, negative charge pump circuit in an N-well CMOS process with all PMOS transistors. The negative charge pump circuit according to the present invention…
Power-up/interrupt delay timer
Granted: June 8, 1999
Patent Number:
5910739
A delay for short power interruptions by using a first comparator to compare the power supply voltage to a voltage reference. A second comparator has a first input coupled to the same voltage reference, and an output which generates the reset signal. A capacitor coupled to the second input of the second comparator determines when a reset signal is issued. The capacitor is normally charged by a current source. When the power supply falls below a set point indexed to the reference voltage,…
Power supply control techniques for FET circuits
Granted: March 9, 1999
Patent Number:
5880623
Method and circuitry for power control in integrated circuits using field effect transistor (FET) technology are disclosed. According to the present invention, for each circuit block that is biased by the power supply voltage a dedicated level shifter is inserted between the block and the power supply. In one embodiment, a switch is also coupled in parallel to the level shifter. The switch is closed when a low external power supply voltage is applied, and opened when a higher power…
Pipeline ADC common-mode tracking circuit
Granted: March 9, 1999
Patent Number:
5880690
A common-mode feedback circuit which calculates the common-mode signal at each stage of a pipeline ADC, rather than calculating it globally and distributing it. The local calculation thus provides a local interpolation between the positive and negative voltage reference, and also provides a mechanism for storing the interpolated charge for application to the common-mode feedback input of the amplifier.
Phase-frequency lock detector
Granted: February 9, 1999
Patent Number:
5870002
A method and circuitry for detecting when a PLL achieves phase and frequency-lock to a reference frequency with minimal hardware and power dissipation are disclosed. The invention takes advantage of existing blocks within a PLL to reduce the amount of circuitry required while at the same time reducing error due to mismatch. In one embodiment, the present invention combines a coarse lock-detect circuit with a fine lock-detect circuit to achieve fast response when the input reference is…
Replica bias circuit to optimize swing of differential op-amp
Granted: January 26, 1999
Patent Number:
5864257
A replica circuit derived from the bias generating circuit for an amplifier. The replica circuit duplicates the operating point of the op-amp transistors, and generates two reference voltages. The average of these two voltages is the optimum common-mode desired output level to maximize differential op-amp swing. Several circuits are disclosed that make use of these two voltages to set the op-amp output to the average of the two voltages.
