Programmable low drift reference voltage generator
Granted: December 22, 1998
Patent Number:
5852360
A reference voltage generating method and circuit is disclosed where the output can be programmably calibrated for minimum temperature drift. Output calibration is performed by adjusting a value of resistance of a resistor in a band-gap circuit. Digitally programmable switches are used to incrementally reduce or increase the value of the target resistor. The control circuit according to the present invention is also designed such that it tracks variations in process and temperature.
Low noise low power CMOS correlated double sampler
Granted: December 1, 1998
Patent Number:
5844431
An improved CMOS CDS circuit which can operate on 2.7 volts, provides increased noise immunity and can handle a 0.8 volts maximum signal input. The present invention provides internal capacitors to isolate the input pads. The present invention also provides switches and capacitors to perform a sample and hold function on every pixel value.
Analog to digital converter having dynamically controlled non-linear output
Granted: October 27, 1998
Patent Number:
5828330
The output of an analog to digital converter is selectively controlled to provide a non-linear response by addition or removal of current from resistors in the ADC reference level resistor ladder so that voltage drops are reduced or increased across selected resistors. In one embodiment a current mirror is employed to remove current at selected nodes of the resistor ladder. Span current and current mirror current can be controlled so that span and the desired non-linearity will track…
Power-up/interrupt delay timer
Granted: October 6, 1998
Patent Number:
5818271
A delay for short power interruptions by using a first comparator to compare the power supply voltage to a voltage reference. A second comparator has a first input coupled to the same voltage reference, and an output which generates the reset signal. A capacitor coupled to the second input of the second comparator determines when a reset signal is issued. The capacitor is normally charged by a current source. When the power supply falls below a set point indexed to the reference voltage,…
Offset-free resistor geometry for use in piezo-resistive pressure sensor
Granted: September 22, 1998
Patent Number:
5812047
An improved resistor and connection region structure in which the geometries of the connection regions for a pair of radial resistors correspond to the connection region geometries for a pair of tangential resistors, thus inherently eliminating the need for varying connection regions to compensate for offset. In particular, the radial resistors are formed by placing two legs in parallel with each other and connecting those legs in series on opposite sides of the membrane, with the…
Voltage level converter with independently adjustable rise and fall delays
Granted: September 8, 1998
Patent Number:
5805005
A voltage level converter circuit is presented that is capable of independently adjusting the falling edge and rising edge delays of the output signal. The circuit includes two separate transconductance amplifiers each biased independently. Each one of the transconductance amplifiers separately drives an output transistor. The circuit is particularly suited for converting ECL signals to CMOS logic levels.
Variable gain peak detector
Granted: September 1, 1998
Patent Number:
5801587
An improved peak detector for an audio limiter is disclosed where the audio limiter comprises preferably a voltage controlled amplifier and the feedback detector in a feedback arrangement. The peak detector has a resistive capacitive load and either charges or discharges more rapidly when the difference between the output of the peak detector and the output of the voltage controlled amplifier increases. As a result, over much of the range of operation of that difference, the charging or…
Voltage-controlled oscillator capable of operating at lower power supply voltages
Granted: September 1, 1998
Patent Number:
5801593
An improved voltage controlled oscillator circuit is based on a multivibrator design with an internal gain stage to permit low voltage operation. An internal gain stage maintains a loop gain of greater than one to ensure oscillation even at power supply voltages as low as 2.7 volts. The added gain allows the use of resistors inserted on either sides of a timing capacitor for improved linearity.
CCD signal digitizing integrated circuit
Granted: August 18, 1998
Patent Number:
5796361
Various innovative circuit techniques that make possible a single chip, cost effective implementation of a CCD signal digitizing circuit are disclosed. Among the various features of the single chip digitizing circuit is the use of a single clock to sample the CCD signal and to digitize the analog signal. By providing a tight control over the minimum required settling time delay at the input of the analog to digital converter (ADC), the speed of the circuit is optimized. Other features…
Voltage multiplier with adjustable output level
Granted: August 4, 1998
Patent Number:
5790393
A circuit and method for generating a fractional multiple of a primary power supply voltage is disclosed. The circuit operates in two phases wherein during a first phase a first capacitor is charged to the primary power supply voltage Vdd, and during a second phase the voltage on the first capacitor is bootstrapped toward twice the power supply voltage. A second capacitor, however, is coupled in parallel to the first capacitor during the second phase to cause charge sharing. The circuit…
RLL to NRZ decoder circuit in disk drive read/write channel
Granted: January 13, 1998
Patent Number:
5708536
The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock.…
Piece-wise linear approximation of a dB linear programmable gain amplifier
Granted: December 30, 1997
Patent Number:
5703524
A programmable gain amplifier which can be realized using CMOS transistors. The amplifier provides a plurality of linear gain segments, with each of the gain segments having a different gain. A particular combination of the gain segments are selected using a digital control input to give an approximation of a linear dB output. By appropriately choosing the segments and how they combine, an approximation that is accurate to the least significant bit of a digital system can be provided.
Switching shunt regulator
Granted: December 16, 1997
Patent Number:
5698970
A shunting regulator which is configured to act as a switch. The regulator includes an enabling input which can be used to turn it on and off when the switch is desired to be closed and opened. Preferably, the regulator includes a switching transistor connected to the enabling input which activates a drive transistor circuit. A current mirror is connected to the regulator output and provides current to both the drive circuit and a differential amplifier used for error correction. The two…
Voltage regulator with differential current steering stage
Granted: December 2, 1997
Patent Number:
5694031
An improved voltage regulator which can operate in a two-lead environment with a widely varying power supply is provided. The voltage regulator of the invention has an output circuit stage connected between a supply voltage and a reference voltage. A pass transistor, as one leg of a differential current steering stage, provides drive current to the output stage. A bandgap error amplifier is coupled between the reference voltage output and the pass transistor to shunt current from the…
Differental D/A converter with N-bits plus sign
Granted: November 18, 1997
Patent Number:
5689259
The present invention provides a digital-to-analog converter which uses two separate digital-to-analog converters for the first N-bits. The N+1 bit, which is the sign bit in a sign and magnitude digital format, is used to provide the difference between the two digital-to-analog converters to the output for a first value, and to switch the DAC outputs for a second value of the sign bit. The present invention thus eliminates the parasitic capacitance of the N+1 bit by using a differential…
V.35 integrated circuit transceiver with diagnostics loopback
Granted: July 15, 1997
Patent Number:
5648972
A single integrated circuit transceiver on a single substrate which can perform synchronous data transmissions that comply with CCITT recommendation V.35 in either the DTE or DCE mode is provided. The same chip can be configured to provide a diagnostics loopback, with the loopback being performed one way for a DTE mode and another way for a DCE mode. The invention provides a simple, elegant solution which minimizes the number of gates and maximizes the benefits.
Low-voltage multi-output current mirror circuit with improved power supply rejection mirrors and method therefor
Granted: April 29, 1997
Patent Number:
5625281
A circuit technique for improving power supply rejection of current mirror circuits having multiple outputs. An input reference current is preadjusted for error caused by power supply variations and then mirrored through a cascade of current mirror circuits. In one embodiment an opamp loop forces the output of a current mirror circuit to be substantially equal to the reference current. This current is then used in subsequent mirroring stages to obtain various outputs. The circuit…
Clock generator using a state machine to switch between two offset clocks
Granted: February 18, 1997
Patent Number:
5604452
A simple structure for switching between two clock signals to produce an output without a glitch or short pulse. The invention is basically a three-input multiplexer controlled by a modified two-bit state machine. The state machine includes flip-flop memories which are driven by the two different clocks, as opposed to using a single clock as in a traditional state machine. The state machine output is used to control the three-input multiplexer, selecting between the first clock, the…
Analog-digital converter using current controlled voltage reference
Granted: January 7, 1997
Patent Number:
5592167
A current driven span voltage source for use in an analog to digital converter includes a zero reference resistor serially connected with a resistor ladder. A first current source selectively passes a part of a first current through the resistor ladder to establish a span (gain) voltage range, and a second current source selectively passes a part of a second current through the zero reference resistor to establish a zero reference voltage for the span voltage range. The controlled…
Power down circuit for use in intergrated circuits
Granted: December 24, 1996
Patent Number:
5587684
A method of including power control features to analog integrated circuits does not require the addition of separate power control input signal pin(s). One or more existing externally applied reference signals are sensed to determine if the signals are within specified operational limits. When the reference signals are outside of the operational limits the internal circuit blocks are switched off to their non-power dissipating state. When the reference signals are within the operational…
