METHODS AND SYSTEMS FOR CONTROL OF SWITCHES IN POWER REGULATORS/POWER AMPLIFIERS
Granted: July 21, 2011
Application Number:
20110175582
A system includes a first switch connected to a voltage input and a switching node. A second switch is connected to the switching node and a reference potential. A first circuit generates first rising edges and first falling edges by comparing a voltage at the switching node to a first voltage reference. The first voltage reference is between the reference potential and the voltage input. A second circuit generates second rising edges and second falling edges by comparing the switching…
WAFER LEVEL STACK DIE PACKAGE
Granted: July 7, 2011
Application Number:
20110163391
This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.
TRANSCEIVER FOR WIRED SERIAL COMMUNICATION
Granted: June 30, 2011
Application Number:
20110161532
This document discusses, among other things, transceiver apparatus and methods for wired serial communication to a remote device. The transceiver can be configured to generate an output signal using received compensation information to maintain a specified signal quality at the remote device. The transceiver can include an input for receiving first information, a compensation input for receiving the compensation information and an output to transmit the output signal including the first…
INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED COMPONENTS
Granted: June 23, 2011
Application Number:
20110147917
This document discusses, among other things, a semiconductor die package having a first and a second discrete components embedded into a dielectric substrate. An integrated circuit (IC) die is surface mounted on a first side of the dielectric substrate. The semiconductor die package includes a plurality of conductive regions on the second side of the dielectric substrate for mounting the semiconductor die package. A plurality of through hole vias couple the IC die to the first and second…
SELECTIVELY ACTIVATED THREE-STATE CHARGE PUMP
Granted: June 23, 2011
Application Number:
20110148385
This document discusses, among other things, a device for providing a DC output voltage, including a first output voltage and a second output voltage, from an input voltage. The device can include a first voltage regulator configured to provide the first output voltage when the input voltage is below a threshold voltage, and a charge pump configured to provide the second output voltage from the first output voltage in a two-state mode when the input voltage is below the threshold…
FAST RECOVERY VOLTAGE REGULATOR
Granted: June 23, 2011
Application Number:
20110148386
This document discusses, among other things, a voltage regulator having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current using a comparison of a regulated Dc output voltage to at least one reference voltage.
REDUCED CURRENT CHARGE PUMP
Granted: June 23, 2011
Application Number:
20110148510
This document discusses, among other things, a charge pump having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current for a capacitor using a comparison of an output voltage to at least one reference voltage.
SiP SUBSTRATE
Granted: June 9, 2011
Application Number:
20110133318
Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger…
STEPPED-SOURCE LDMOS ARCHITECTURE
Granted: June 2, 2011
Application Number:
20110127607
A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and…
METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES
Granted: May 26, 2011
Application Number:
20110124197
A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.
THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE
Granted: May 26, 2011
Application Number:
20110124158
A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with…
WAFER LEVEL SEMICONDUCTOR DEVICE CONNECTOR
Granted: April 28, 2011
Application Number:
20110095410
This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be activated to conductive plating deposition using laser ablation.
LEADLESS SEMICONDUCTOR DEVICE TERMINAL
Granted: April 28, 2011
Application Number:
20110095417
This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.
METHOD OF DETECTING ACCESSORIES ON AN AUDIO JACK
Granted: April 28, 2011
Application Number:
20110099298
An apparatus comprises an audio or video jack connector configured to receive an audio or video jack plug of a separate device, a detection circuit in electrical communication with the connector, and a processor communicatively coupled to the detection circuit. The connector includes an electrical contact for connection to a conducting terminal of the plug. The detection circuit is configured to determine a resistance at the conducting terminal. The resistance is a resistive load of the…
CAMERA SHUTTER CONTROL THROUGH A USB PORT OR AUDIO/VIDEO PORT
Granted: April 28, 2011
Application Number:
20110099300
An apparatus comprises a digital image sensor, a communication port, a detection circuit and a processor. The detection circuit is configured to detect a change in electrical resistance at a connector of the communication port. The processor is configured to initiate an operation of the apparatus according to the detected change in resistance.
WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE
Granted: April 21, 2011
Application Number:
20110089432
An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.
EMBEDDED DIE PACKAGE AND PROCESS FLOW USING A PRE-MOLDED CARRIER
Granted: March 24, 2011
Application Number:
20110068461
An embedded die package includes a carrier with an electrical device in the cavity of the carrier, a first dielectric layer covering the sides and top of the electrical device except for vias over selected bonding pads of the electrical device, a plurality of metal conductors, each of which is in contact with at least one of the vias, one or more additional dielectric layers lying over the metal conductors and the first dielectric layer, wherein a top layer of the one or more dielectric…
3D SMART POWER MODULE
Granted: March 24, 2011
Application Number:
20110070699
A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semiconductor devices are die bonded to a direct bonded copper substrate which has a bottom surface exposed in the molded package. In one embodiment the module has 27 external connectors attached to one side of the PC board and…
METHOD AND APPARATUS FOR BONDED SUBSTRATES
Granted: February 24, 2011
Application Number:
20110042013
An apparatus for bonding substrates includes a base member having a top surface and a recessed region which is configured for receiving at least a first substrate. The apparatus also has a plurality of support members disposed over the top surface for supporting a second substrate peripherally over the first substrate. Each support member is configured to vary a separation between the first substrate and the second substrate. Moreover, a pressure bar is configured to cause a center…
INTEGRATED LOW LEAKAGE DIODE
Granted: February 24, 2011
Application Number:
20110042717
An integrated low leakage diode suitable for operation in a power integrated circuit has a structure similar to a lateral power MOSFET, but with the current flowing through the diode in the opposite direction to a conventional power MOSFET. The anode is connected to the gate and the comparable MOSFET source region which has highly doped regions of both conductivity types connected to the channel region to thereby create a lateral bipolar transistor having its base in the channel region.…
