IGNITION SYSTEM OPEN SECONDARY DETECTION
Granted: February 10, 2011
Application Number:
20110031979
This document discusses, among other things, a system and method for detecting an open secondary condition in a secondary coil of an ignition coil using a control signal received from a control input of a switch configured to control the flow of current to a primary coil of the ignition coil. In an example, the flow of current in the primary coil of the ignition coil can be controlled using an insulated gate bipolar junction transistor (IGBT), and the open secondary condition in the…
NO POP SWITCH
Granted: January 13, 2011
Application Number:
20110010750
A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.
SEMICONDUCTOR DIE PACKAGE INCLUDING LEADFRAME WITH DIE ATTACH PAD WITH FOLDED EDGE
Granted: January 13, 2011
Application Number:
20110008935
A semiconductor die package is disclosed. The semiconductor die package comprises a leadframe structure with a die attach pad including a die attach surface, a folded edge structure and an opposite surface opposite to the die attach surface. A plurality of leads extending laterally away from the die attach pad. A semiconductor die comprising a first surface and a second surface is attached to the semiconductor die, and a molding material is around at least a portion of the leadframe…
FLIP CHIP MLP WITH FOLDED HEAT SINK
Granted: January 6, 2011
Application Number:
20110003432
A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat sink has a planar member generally coextensive in size with the MLP and in electrical and thermal contact with the top emitter pad of the MLP, and also has one or more leads extending generally perpendicularly to the planar…
PN JUNCTION AND MOS CAPACITOR HYBRID RESURF TRANSISTOR
Granted: December 23, 2010
Application Number:
20100323485
A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current…
HIGH SPEED, LOW POWER CONSUMPTION, ISOLATED ANALOG CMOS UNIT
Granted: December 16, 2010
Application Number:
20100315155
A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating…
UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO
Granted: December 16, 2010
Application Number:
20100318704
This document discusses, among other things, a system and method for switching serialized video information (e.g., non-packet-based video information) and Universal Serial Bus (USB) information (e.g., packet-based information) to a common output (e.g., to a physical USB interface).
UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO
Granted: December 16, 2010
Application Number:
20100318697
This document discusses, among other things, a system and method for deserializing non-packet-based video information received using a physical Universal Serial Bus (USB) interface and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information.
SELF-ALIGNED COMPLEMENTARY LDMOS
Granted: October 21, 2010
Application Number:
20100267213
The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version…
INTEGRATED LOW LEAKAGE SCHOTTKY DIODE
Granted: September 16, 2010
Application Number:
20100233862
An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are…
QUASI-RESURF LDMOS
Granted: September 2, 2010
Application Number:
20100219471
A semiconductor device can include a drift region, at least a portion of the drift region located laterally between a drain region and a source region. The drift region can include a first layer having a first doping concentration and a second layer having a second higher doping concentration than the first layer. The second layer of the drift region be configured to allow drift current between the source region and the drain region when a depletion region is formed in at least a portion…
PERIPHERAL DEVICE HOST CHARGING
Granted: September 2, 2010
Application Number:
20100219790
This document discusses, among other things, a charging emulator configured to be coupled to an electrical interface, the charging emulator including a control circuit configured to receive information about a peripheral device coupled to the electrical interface and a charger circuit configured to provide power to the electrical interface using the received peripheral device information. In an example, the charging emulator can include a component of a host device including a low-power…
Devices, Methods, and Systems With MOS-Gated Trench-to-Trench Lateral Current Flow
Granted: August 5, 2010
Application Number:
20100194467
A DMOS transistor is fabricated with its source/body/deep body regions formed on the walls of a first set of trenches, and its drain regions formed on the walls of a different set of trenches. A gate region that is formed in a yet another set of trenches can be biased to allow carriers to flow from the source to the drain. Lateral current low from source/body regions on trench walls increases the active channel perimeter to a value well above the amount that would be present if the…
POWER QUAD FLAT NO-LEAD SEMICONDUCTOR DIE PACKAGES WITH ISOLATED HEAT SINK FOR HIGH-VOLTAGE, HIGH-POWER APPLICATIONS, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME
Granted: June 17, 2010
Application Number:
20100148328
Disclosed are PQFN semiconductor die packages for high-voltage, high-power applications, systems using the packages, and methods of making the packages. An exemplary package comprises a leadframe, a semiconductor die disposed on the leadframe, and a heat sink member disposed on the semiconductor die and the leadframe and integrated into the molding material of the package. The heat sink member has an electrically insulating substrate with a high breakdown voltage, and one or more…
SEMICONDUCTOR STRUCTURES FORMED ON SUBSTRATES AND METHODS OF MANUFACTURING THE SAME
Granted: March 4, 2010
Application Number:
20100052046
A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a…
AMPLIFIER CURRENT DRIVE REVERSAL
Granted: January 7, 2010
Application Number:
20100001799
A drive current direction between first and second amplifiers can be selected using a received indication of an output current in an at least partially reactive load, and an amplified output signal can be produced using the selected drive current direction and the first and second amplifiers. Further, the first and second amplifiers can be configured to alternate between a pull-up mode and a pull-down mode, each amplifying half of a full wave output signal.
THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE
Granted: March 19, 2009
Application Number:
20090072362
A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with…
METHOD AND DEVICE WITH DURABLE CONTACT ON SILICON CARBIDE
Granted: September 18, 2008
Application Number:
20080227275
A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.
High voltage LDMOS
Granted: September 4, 2008
Application Number:
20080210974
A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial…
ULTRA DENSE TRENCH-GATED POWER DEVICE WITH THE REDUCED DRAIN-SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE
Granted: September 4, 2008
Application Number:
20080211014
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The…
