ULTRA DENSE TRENCH-GATED POWER DEVICE WITH REDUCED DRAIN SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE
Granted: June 19, 2008
Application Number:
20080142909
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The…
HIGH VOLTAGE LDMOS
Granted: June 12, 2008
Application Number:
20080138954
A semiconductor device, such as a LDMOS device, comprising: a semiconductor substrate; a drain region in the semiconductor substrate; a source region in the semiconductor substrate laterally spaced from the drain region; and a drift region in the semiconductor substrate between the drain region and the source region. A gate is operatively coupled to the source region and is located offset from the drain region on a side of the source region opposite from the drain region. When the device…
MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME
Granted: May 29, 2008
Application Number:
20080121989
An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer…
MOS-GATED DEVICE HAVING A BURIED GATE AND PROCESS FOR FORMING SAME
Granted: May 22, 2008
Application Number:
20080116510
An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer…
LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE
Granted: January 17, 2008
Application Number:
20080014764
A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours.
METHOD OF DRIVING A DUAL GATED MOSFET
Granted: July 5, 2007
Application Number:
20070152729
A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the…
Power mosfet and method for forming same using a self-aligned body implant
Granted: August 25, 2005
Application Number:
20050184318
A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the…
Power semiconductor devices and methods of manufacture
Granted: August 4, 2005
Application Number:
20050167742
Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another…
Filp chip in leaded molded package and method of manufacture thereof
Granted: August 4, 2005
Application Number:
20050167848
A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
Method of manufacturing a trench transistor having a heavy body region
Granted: April 14, 2005
Application Number:
20050079676
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the…
Flip chip substrate design
Granted: March 10, 2005
Application Number:
20050051878
A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.
METHOD FOR FORMING SEMICONDUCTOR DEVICE INCLUDING STACKED DIES
Granted: January 6, 2005
Application Number:
20050001293
A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.
Passivation scheme for bumped wafers
Granted: December 2, 2004
Application Number:
20040241977
A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered altematingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.
Power MOS device with improved gate charge performance
Granted: November 25, 2004
Application Number:
20040232407
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the…
Carrier with metal bumps for semiconductor die packages
Granted: November 25, 2004
Application Number:
20040232542
A carrier for a semiconductor die package is disclosed. In one embodiment, the carrier includes a metal layer and a plurality of bumps formed in the metal layer. The bumps can be formed by stamping.
Flip chip in leaded molded package with two dies
Granted: October 14, 2004
Application Number:
20040201086
A chip device including two stacked dies. The chip device includes a leadframe that includes a plurality of leads. A first die is coupled to a first side of the leadframe with solder and a second die is coupled to a second side of the leadframe with solder. A molded body surrounds at least a portion of the leadframe and the dies.
Unmolded package for a semiconductor device
Granted: August 26, 2004
Application Number:
20040164386
A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while…
High performance multi-chip flip chip package
Granted: August 19, 2004
Application Number:
20040159939
A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon…
Field effect transistor and method of its manufacture
Granted: July 29, 2004
Application Number:
20040145015
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the…
Semiconductor die including conductive columns
Granted: July 15, 2004
Application Number:
20040137724
A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.
