ESD PROTECTION CIRCUIT FOR INSIDE A POWER PAD OR INPUT/OUTPUT PAD
Granted: April 30, 2009
Application Number:
20090109583
An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that…
Low Power Output Driver
Granted: April 23, 2009
Application Number:
20090102513
A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first,…
Multi-Function Queue To Support Data Offload, Protocol Translation And Pass-Through FIFO
Granted: April 2, 2009
Application Number:
20090086748
A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first…
Non-Random Access Rapid I/O Endpoint In A Multi-Processor System
Granted: April 2, 2009
Application Number:
20090086750
A system and method for using a doorbell command to allow sRIO devices to operate as bus masters to retrieve data packets stored in a serial buffer, without requiring the SRIO devices to specify the sizes of the data packets. The serial buffer includes a plurality of queues that store data packets. A doorbell frame request packet identifies the queue to be accessed within the serial buffer, but does not specify the size of the data packet(s) to be retrieved. Upon detecting a doorbell…
Adaptive Interrupt On Serial Rapid Input/Output (SRIO) Endpoint
Granted: April 2, 2009
Application Number:
20090086751
A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with…
Serial Buffer Supporting Virtual Queue To Physical Memory Mapping
Granted: April 2, 2009
Application Number:
20090089532
A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port…
Synchronous Address And Data Multiplexed Mode For SRAM
Granted: April 2, 2009
Application Number:
20090089538
A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable…
Input Clock Detection Circuit for Powering Down a PLL-Based System
Granted: October 2, 2008
Application Number:
20080238508
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the…
Simple Technique For Reduction Of Gain In A Voltage Controlled Oscillator
Granted: October 2, 2008
Application Number:
20080238556
A ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage, while the remaining inverter stages are operated in response to a highly filtered constant input voltage. The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response…
PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET
Granted: September 11, 2008
Application Number:
20080218274
A control circuit includes a phase frequency detector that receives a reference phase ?REF (signal) as an input and a feedback phase ?FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase ?FBK (signal). An auxiliary feedback loop receives error phase ?E (signal) from each of the reference phase ?REF (signal) and the feedback phase ?FBK (signal). The auxiliary…
Switching Circuit Implementing Variable String Matching
Granted: September 4, 2008
Application Number:
20080212581
A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can be linked by per-entry counters associated with each string, or by a state machine. The strings in the CAM array are compared with a packet, which is shifted one symbol at a time (because the strings can…
Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol
Granted: August 28, 2008
Application Number:
20080205422
On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow…
Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer
Granted: August 28, 2008
Application Number:
20080205438
A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations).…
Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface
Granted: August 28, 2008
Application Number:
20080209084
A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data…
Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port
Granted: August 28, 2008
Application Number:
20080209089
A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a…
Rapid Input/Output Doorbell Coalescing To minimize CPU Utilization And Reduce System Interrupt Latency
Granted: August 28, 2008
Application Number:
20080209139
Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be…
Modular Distributive Arithmetic Logic Unit
Granted: July 10, 2008
Application Number:
20080168256
A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data…
Using A Delay Clock To Optimize The Timing Margin Of Sequential Logic
Granted: June 19, 2008
Application Number:
20080143383
A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay…
Input Termination For Delay Locked Loop Feedback With Impedance Matching
Granted: June 12, 2008
Application Number:
20080136443
A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as…
Common Access Ring System
Granted: June 12, 2008
Application Number:
20080140891
A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no…
