Common Access Ring/Sub-Ring System
Granted: June 12, 2008
Application Number:
20080140892
A common access ring (CAR) architecture that supports multiple masters and slaves is provided. One or more masters may make a request on the ring at the same time, such that multiple transactions are simultaneously pending. Moreover, multiple masters may simultaneously make a request to the same slave. However, each master cannot make more than one request at a time, and must wait until a current request is completed before making another request. The ring architecture ensures that no…
Multi-Finger Capacitor
Granted: June 5, 2008
Application Number:
20080128857
A multi-finger capacitor structure includes a capacitor input node having a first set of conductive fingers, a capacitor output node having a second set of conductive fingers interleaved with the first set of conductive fingers, and a conductive plate and/or pattern connected to the capacitor input node, and located between a substrate and the first and second sets of interleaved conductive fingers. The conductive plate/pattern renders the parasitic capacitance of the capacitor output…
Output Slew Rate Control In Low Voltage Differential Signal (LVDS) Driver
Granted: June 5, 2008
Application Number:
20080129349
A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with…
Low Power Logic Output Buffer
Granted: May 29, 2008
Application Number:
20080122487
A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and…
LOW POWER OUTPUT DRIVER
Granted: February 28, 2008
Application Number:
20080048724
A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first,…
MINIMIZING TIMING SKEW AMONG CHIP LEVEL OUTPUTS FOR REGISTERED OUTPUT SIGNALS
Granted: October 11, 2007
Application Number:
20070236249
A synchronous output buffer circuit which effectively moves combinational logic associated with an output enable operation, boundary scan operation, and voltage translation to a pipe that leads into a pair of output registers that operate in response to the output clock signal. The output registers may be forced to asynchronously route an input signal to an output terminal during a reset mode and during a boundary scan mode. The output registers can include a safety circuit, which…
Auto-Adaptive Digital Phase-Locked Loop for Large Frequency Multiplication Factors
Granted: October 4, 2007
Application Number:
20070230650
An auto-adaptive digital phase locked loop (DPLL) includes a phase detector comprising an edge detector having an input that receives an input clock, and an output that outputs a reference event generated from a reference edge of the input clock. The DPLL also includes a programmable first counter that counts down at the generated clock rate, the first counter having a first input that is programmed with an integer value M, a second input that receives the generated clock, and an output…
Data Output Clock Selection Circuit For Quad-Data Rate Interface
Granted: October 4, 2007
Application Number:
20070234251
A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have the same predetermined value. The activated reset control signal asynchronously resets a pair of series connected flip-flops. The deactivated reset control…
Method and apparatus for pre-clocking
Granted: June 21, 2007
Application Number:
20070139091
A method and apparatus for pre-clocking have been disclosed.
Switching circuit implementing variable string matching
Granted: April 12, 2007
Application Number:
20070083646
A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can be linked by per-entry counters associated with each string, or by a state machine. The strings in the CAM array are compared with a packet, which is shifted one symbol at a time (because the strings can…
Method and apparatus for predictive switching
Granted: February 8, 2007
Application Number:
20070030938
A method and apparatus for predictive switching an output have been disclosed.
Method and apparatus for parameter adjustment, testing, and configuration
Granted: January 18, 2007
Application Number:
20070016835
A method and apparatus for parameter monitoring, adjustment, testing, and/or configuration of devices have been disclosed.
Method and apparatus for source synchronous testing
Granted: December 28, 2006
Application Number:
20060294411
A method and apparatus for source synchronous testing have been disclosed.
Low power content addressable memory array (CAM) and method of operating same
Granted: May 11, 2006
Application Number:
20060098468
A content addressable memory (CAM) system that includes a row of NAND-type CAM cells divided into a plurality of segments. Each segment includes a plurality of series-connected switching transistors, wherein each of the switching transistors is part of a corresponding NAND-type CAM cell. The series-connected switching transistors of each segment are coupled to the series-connected switching transistors in an adjacent segment by a repeater circuit, thereby forming a chain of…
Fast collision detection for a hashed content addressable memory (CAM) using a random access memory
Granted: May 4, 2006
Application Number:
20060095654
A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, provides an index value and activates a hit signal if the hashed output value matches an entry of the CAM. A random access memory (RAM) receives the index value from the CAM. The RAM stores a collision resolution value and…
Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device
Granted: April 20, 2006
Application Number:
20060083185
A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.
Method and apparatus for processing a complete burst of data
Granted: February 23, 2006
Application Number:
20060039284
Disclosed are a method and apparatus for processing a complete burst of data by receiving said complete burst of data, storing the complete burst of data in a memory, associating the complete burst of data with a first logical channel and dispatching an egress burst of data according to one or more complete bursts of data stored in a memory and associated with the first logical channel.
Memory array bit line coupling capacitor cancellation
Granted: February 9, 2006
Application Number:
20060028860
Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the…
Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060017497
A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit…
Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060018170
A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory…
