Method of forming package structure
Granted: April 9, 2024
Patent Number:
11951571
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the…
MRAM access coordination systems and methods via pipeline in parallel
Granted: March 26, 2024
Patent Number:
11941299
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a…
High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices
Granted: March 5, 2024
Patent Number:
11925125
The disclosure provides a magnetic random access memory element. The magnetic random access memory element includes a magnetic reference layer, a magnetic free layer, and a non-magnetic barrier layer between the magnetic free layer and the magnetic reference layer. The magnetic random access memory element further includes a MgO layer contacting the magnetic free layer. The MgO layer includes multiple homogeneous layers of MgO that provide excellent interfacial perpendicular magnetic…
Power management circuit in low-power double data rate memory and management method thereof
Granted: February 6, 2024
Patent Number:
11894043
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power…
Controlling circuit for low-power low dropout regulator and controlling method thereof
Granted: December 12, 2023
Patent Number:
11841722
A controlling circuit for a low-power low dropout regulator includes the low-power low dropout regulator, a current load detector and a bias current circuit. The low-power low dropout regulator has a first transmitting terminal and a second transmitting terminal. The first transmitting terminal is configured to transmit a first voltage, the second transmitting terminal is configured to transmit a second voltage, and the low-power low dropout regulator adjusts a voltage difference between…
System and method for classifying data using neural networks with errors
Granted: December 5, 2023
Patent Number:
11836607
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using…
Compact and efficient CMOS inverter
Granted: June 27, 2023
Patent Number:
11688649
A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+…
Patterned silicide structures and methods of manufacture
Granted: April 18, 2023
Patent Number:
11631807
Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide…
DRAM with selective epitaxial cell transistor
Granted: April 11, 2023
Patent Number:
11626407
A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly…
Multi terminal device stack formation methods
Granted: April 11, 2023
Patent Number:
11626559
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals…
SPI NOR memory with optimized read and program operation
Granted: April 11, 2023
Patent Number:
11626149
A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
MRAM architecture with multiplexed sense amplifiers and direct write through buffers
Granted: April 4, 2023
Patent Number:
11621027
A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
MRAM architecture with multiplexed sense amplifiers and direct write through buffers
Granted: April 4, 2023
Patent Number:
11621027
A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source…
FINFET stack gate memory and method of forming thereof
Granted: March 28, 2023
Patent Number:
11616145
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG…
Method of forming package structure
Granted: March 28, 2023
Patent Number:
11612965
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the…
High density spin orbit torque magnetic random access memory
Granted: March 7, 2023
Patent Number:
11600769
A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin…
Error cache system with coarse and fine segments for power optimization
Granted: February 21, 2023
Patent Number:
11586553
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary…
System and method for training artificial neural networks
Granted: February 21, 2023
Patent Number:
11586906
A computing device receives first data on which to train an artificial neural network (ANN). Using magnetic random access memory (MRAM), the computing device trains the ANN by performing a first set of training iterations on the first data. Each of the first set of iterations includes writing values for a set of weights of the ANN to the MRAM using first write parameters corresponding to a first write error rate. After performing the first set of iterations, the computing device performs…
