Signal synchronization adjustment method and signal synchronization adjustment circuit
Granted: October 15, 2024
Patent Number:
12119041
The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising…
Precessional spin current structure with non-magnetic insertion layer for MRAM
Granted: August 27, 2024
Patent Number:
12075706
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second…
Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
Granted: August 20, 2024
Patent Number:
12069964
A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of…
Method for manufacturing a magnetic random-access memory device using post pillar formation annealing
Granted: August 20, 2024
Patent Number:
12069957
A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both…
Multi terminal device stack systems and methods
Granted: July 2, 2024
Patent Number:
12029045
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; a…
Wafer-bonding structure and method of forming thereof
Granted: June 25, 2024
Patent Number:
12021059
A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side…
Method of forming package structure
Granted: April 9, 2024
Patent Number:
11951571
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the…
MRAM access coordination systems and methods via pipeline in parallel
Granted: March 26, 2024
Patent Number:
11941299
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a…
High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices
Granted: March 5, 2024
Patent Number:
11925125
The disclosure provides a magnetic random access memory element. The magnetic random access memory element includes a magnetic reference layer, a magnetic free layer, and a non-magnetic barrier layer between the magnetic free layer and the magnetic reference layer. The magnetic random access memory element further includes a MgO layer contacting the magnetic free layer. The MgO layer includes multiple homogeneous layers of MgO that provide excellent interfacial perpendicular magnetic…
Power management circuit in low-power double data rate memory and management method thereof
Granted: February 6, 2024
Patent Number:
11894043
A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power…
Controlling circuit for low-power low dropout regulator and controlling method thereof
Granted: December 12, 2023
Patent Number:
11841722
A controlling circuit for a low-power low dropout regulator includes the low-power low dropout regulator, a current load detector and a bias current circuit. The low-power low dropout regulator has a first transmitting terminal and a second transmitting terminal. The first transmitting terminal is configured to transmit a first voltage, the second transmitting terminal is configured to transmit a second voltage, and the low-power low dropout regulator adjusts a voltage difference between…
System and method for classifying data using neural networks with errors
Granted: December 5, 2023
Patent Number:
11836607
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using…
Compact and efficient CMOS inverter
Granted: June 27, 2023
Patent Number:
11688649
A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+…
Patterned silicide structures and methods of manufacture
Granted: April 18, 2023
Patent Number:
11631807
Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide…
Multi terminal device stack formation methods
Granted: April 11, 2023
Patent Number:
11626559
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals…
DRAM with selective epitaxial cell transistor
Granted: April 11, 2023
Patent Number:
11626407
A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly…
SPI NOR memory with optimized read and program operation
Granted: April 11, 2023
Patent Number:
11626149
A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output…
MRAM architecture with multiplexed sense amplifiers and direct write through buffers
Granted: April 4, 2023
Patent Number:
11621027
A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
