Multi terminal device stack formation methods
Granted: April 11, 2023
Patent Number:
11626559
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals…
DRAM with selective epitaxial cell transistor
Granted: April 11, 2023
Patent Number:
11626407
A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly…
SPI NOR memory with optimized read and program operation
Granted: April 11, 2023
Patent Number:
11626149
A serial NOR memory device receives serial input data using a single data rate (SDR) mode and transmits serial output data using a double data rate (DDR) mode. In some embodiments, a serial NOR memory device includes an input-output circuit including a transceiver coupled to receive a clock signal and serial input data and to provide serial output data. The transceiver is configured to receive serial input data using the single data rate mode and is configured to transmit serial output…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
MRAM architecture with multiplexed sense amplifiers and direct write through buffers
Granted: April 4, 2023
Patent Number:
11621027
A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source…
Multi terminal device stack systems and methods
Granted: April 4, 2023
Patent Number:
11621293
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a…
MRAM architecture with multiplexed sense amplifiers and direct write through buffers
Granted: April 4, 2023
Patent Number:
11621027
A magnetic memory device for storing and quickly retrieving data from an array of magnetic memory elements. The array includes a plurality of magnetic memory element such as magnetic tunnel junction elements arranged in rows and columns. A plurality of multiplexed bit lines is connected with a first end of each of the magnetic memory elements and plurality of multiplexed source lines are connected with a second end of each of the magnetic memory elements. The multiplexing allows source…
FINFET stack gate memory and method of forming thereof
Granted: March 28, 2023
Patent Number:
11616145
A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG…
Method of forming package structure
Granted: March 28, 2023
Patent Number:
11612965
A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the…
High density spin orbit torque magnetic random access memory
Granted: March 7, 2023
Patent Number:
11600769
A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin…
System and method for training artificial neural networks
Granted: February 21, 2023
Patent Number:
11586906
A computing device receives first data on which to train an artificial neural network (ANN). Using magnetic random access memory (MRAM), the computing device trains the ANN by performing a first set of training iterations on the first data. Each of the first set of iterations includes writing values for a set of weights of the ANN to the MRAM using first write parameters corresponding to a first write error rate. After performing the first set of iterations, the computing device performs…
Error cache system with coarse and fine segments for power optimization
Granted: February 21, 2023
Patent Number:
11586553
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary…
Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments
Granted: February 14, 2023
Patent Number:
11580014
A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary…
System and method for training neural networks with errors
Granted: February 7, 2023
Patent Number:
11574194
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data on which to train a neural network comprising at least one quantized layer and performs a set of training iterations to train weights for the neural network. Each training iteration of the set of training iterations includes stochastically writing…
System and method for classifying data using neural networks with errors
Granted: January 31, 2023
Patent Number:
11568222
A computing device includes one or more processors, random access memory (RAM), and a non-transitory computer-readable storage medium storing instructions for execution by the one or more processors. The computing device receives first data and classifies the first data using a neural network that includes at least one quantized layer. The classifying includes reading values from the random access memory for a set of weights of the at least one quantized layer of the neural network using…
Methods of manufacture precessional spin current magnetic tunnel junction devices
Granted: January 3, 2023
Patent Number:
11545620
A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Ru) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.
Selector transistor with continuously variable current drive
Granted: January 3, 2023
Patent Number:
11545524
A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane…
Three-dimensional (3D) magnetic memory devices comprising a magnetic tunnel junction (MTJ) having a metallic buffer layer
Granted: September 27, 2022
Patent Number:
11456410
A magnetic memory device comprises a cylindrical core and a plurality of layers surrounding the core. The plurality of layers include a metallic buffer layer, a ferromagnetic storage layer, a barrier layer, and a ferromagnetic reference layer. The cylindrical core, the metallic buffer layer, the ferromagnetic storage layer, the barrier layer, and the ferromagnetic reference layer collectively form a magnetic tunnel junction. A magnetization of the ferromagnetic layer storage parallels an…
Arbitration control for pseudostatic random access memory device
Granted: September 13, 2022
Patent Number:
11442875
An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a…
Selector transistor with metal replacement gate wordline
Granted: September 13, 2022
Patent Number:
11444123
A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure…
