Repetition scheme for flexible bandwidth utilization
Granted: March 10, 2020
Patent Number:
10587365
A network device implements a repetition scheme to generate a repetition-encoded FEC codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of bit sequences concatenated together. The set of bit sequences corresponds to a set of OFDM symbols. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. In one embodiment, a right cyclic…
Domain establishment, registration and resignation via a push button mechanism
Granted: October 8, 2019
Patent Number:
10439674
A network node includes a pushbutton to provide a button-press event and a pairer to receive the button-press event while not being in a secure domain. In response to the button-press, the pairer alternates between acting as an endpoint node and acting as a temporary domain master, until pairing is completed. In an alternative embodiment, the node includes a multi-pairer to receive the button press event and, in response, to open a pairing window, to become a domain master of a secure…
Embedded transconductance test circuit and method for flash memory cells
Granted: October 1, 2019
Patent Number:
10431321
A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.
Secured chip enable with chip disable
Granted: June 25, 2019
Patent Number:
10331575
A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where…
Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
Granted: March 19, 2019
Patent Number:
10236042
A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having…
Memory device read training method
Granted: March 12, 2019
Patent Number:
10229743
A memory device implements a memory read training method using a dedicated read command to retrieve training data from a register for performing memory read training while the memory device remains operating in the normal operation mode. Subsequent to the memory read training, the memory device may then receive the normal read command to read data from the memory cell array or the normal write command to write data to the memory cell array. In this manner, memory read training is…
Method for forming flash memory unit
Granted: January 1, 2019
Patent Number:
10170597
A method for forming flash memory units is provided. After a logic gate in a select gate PMOS transistor area is separated from a logic gate in a control gate PMOS transistor area, P-type impurities implanted into the logic gate in the select gate PMOS transistor area are diffused into an N-type floating gate polysilicon layer to convert the N-type floating gate into a P-type floating gate by a subsequent high temperature heating process, so that it is possible to successfully form a…
Calibration circuit for on-chip drive and on-die termination
Granted: October 16, 2018
Patent Number:
10103731
Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed…
Clocked commands timing adjustments in synchronous semiconductor integrated circuits
Granted: September 4, 2018
Patent Number:
10068626
A clock timing adjust circuit is incorporated in a clocked integrated circuit to detect an input clock frequency and to adjust the timing latency of an internal control signal for accessing a memory element in the clocked integrated circuit. The clock timing adjust circuit introduces an adjustable timing latency to an internal control signal derived from the command signal. The clock timing adjust circuit operates to adjust the timing latency of the control signal to cause clock based…
Method for operating flash memory
Granted: June 26, 2018
Patent Number:
10008267
The present disclosure relates to semiconductor devices and discloses a method for operating a flash memory. When a read operation is performed on a flash memory unit, a potential of a first control line connected to gates of select gate PMOS transistors located in a same row is switched from a positive supply voltage to 0V. Since it is not required to switch the potential from a positive voltage to a negative voltage, the power consumption of the pump circuit is significantly reduced.…
Power supply transient reduction method for multiple LED channel systems
Granted: May 8, 2018
Patent Number:
9967932
An LED controller for a multiple LED channel system using PWM method for LED dimming function incorporates a digital dimming control circuit to generate the PWM signals for driving the LED channels to spread out or cancel out the power supply transients generated by the LED transient current during PWM modulation for dimming operation. The digital dimming control circuit implements a power supply transient reduction method whereby the active period of the PWM signals for some of the LED…
Serial bus event notification in a memory device
Granted: February 27, 2018
Patent Number:
9904596
A memory device incorporates a serial data bus coupled to a serial bus control circuit to provide access to error correction event notification information and error correction function configuration information. In some embodiments, the serial bus control circuit is in communication with a set of registers storing error correction event information and error correction function configuration information. The serial data bus enables access to the error correction control functions and to…
Serial bus DRAM error correction event notification
Granted: January 30, 2018
Patent Number:
9880901
A memory device incorporates a serial data bus coupled to the control circuit of the memory device to provide direct access to the error correction control circuit and to the error correction event notification information and error correction function configuration information stored in mode registers of the control circuit. The serial data bus enables access to the error correction control functions and to the error correction event notification information without requiring…
Calibration circuit for on-chip drive and on-die termination
Granted: October 3, 2017
Patent Number:
9780785
Calibration circuits and methods to set an on-chip impedance to match a target impedance where the reference voltage does not equal one-half of the positive power supply voltage Vddq are described. In particular, calibration circuits and methods are provided to enable accurate impedance matching at a reference voltage Vref of K*Vddq, where K is a number between 0 and 1. In some embodiments, a calibration circuit for impedance matching at a reference voltage of K*Vddq uses a ratioed…
Audible noise reduction method for multiple LED channel systems
Granted: July 25, 2017
Patent Number:
9717123
An LED controller for a multiple LED channel system using PWM method for LED dimming function incorporates a digital dimming control circuit to generate the PWM signals for driving the LED channels to spread out or cancel out the power supply transients generated by the LED transient current during PWM modulation for dimming operation. The digital dimming control circuit implements an audible noise reduction method whereby the active period of the PWM signals for some of the LED channels…
Low power high speed program method for multi-time programmable memory device
Granted: June 6, 2017
Patent Number:
9672923
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present…
Low power high speed program method for multi-time programmable memory device
Granted: January 10, 2017
Patent Number:
9543016
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present…
DRAM error correction event notification
Granted: December 27, 2016
Patent Number:
9529667
A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the accessed memory location in the first memory array and retrieving error correction check bits corresponding to the accessed memory location from the second memory array; checking the retrieved memory data for bit errors using the…
Auto low current programming method without verify
Granted: December 6, 2016
Patent Number:
9514806
A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low current auto-verification programming scheme performs programming of memory cells by the application of programming voltages in step increments. For each programming pulse, the cell current of the memory cell is sensed to determine when the memory cell is programmed. The programming pulse is terminated when the cell current decreases…
Resistive memory device implementing selective memory cell refresh
Granted: November 15, 2016
Patent Number:
9496030
A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the selective refresh operation introduces a sense margin guardband so that a memory cell having programmed resistance that falls within the sense margin guardband will be refreshed during the read operation. The selective refresh operation is performed transparently at each read cycle of the memory cells and only memory cells with…
