Compact and efficient CMOS inverter
Granted: April 12, 2022
Patent Number:
11302586
A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first…
Precessional spin current structure for magnetic random access memory with novel capping materials
Granted: March 22, 2022
Patent Number:
11283010
A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and…
Precessional spin current structure with nonmagnetic insertion layer for MRAM
Granted: March 8, 2022
Patent Number:
11271149
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second…
High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices
Granted: March 1, 2022
Patent Number:
11264557
A method for manufacturing a magnetic random access memory element having increased retention and low resistance area product (RA). A MgO layer is deposited to contact a magnetic free layer of the memory element. The MgO layer is deposited in a sputter deposition chamber using a DC power and a Mg target to deposit Mg. The deposition of Mg is periodically stopped and oxygen introduced into the deposition chamber. This process is repeated a desired number of times, resulting in a…
Perpendicular magnetic tunnel junction memory cells having vertical channels
Granted: January 11, 2022
Patent Number:
11222970
A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of…
Memory inspecting method and memory inspecting system
Granted: December 7, 2021
Patent Number:
11195592
A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention…
Magnetic field transducer mounting methods for MTJ device testers
Granted: November 2, 2021
Patent Number:
11162981
A magnetic field transducer mounting apparatus can include a first mount configured to fixedly couple to a side surface of a wafer test fixture magnet, and a second and third mount configured to adjustably position a magnetic field transducer in a predetermined location proximate a face of the wafer test fixture magnet.
Error cache segmentation for power reduction
Granted: October 19, 2021
Patent Number:
11151042
A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Also, the cache memory is divided into…
Internal latch circuit and method for generating latch signal thereof
Granted: September 7, 2021
Patent Number:
11115006
An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by…
Repetition scheme for flexible bandwidth utilization
Granted: July 27, 2021
Patent Number:
11075716
A network device implements a repetition scheme to generate a repetition-encoded forward error correction (FEC) codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of N offset-shifted bit sequences. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. The set of N offset-shifted bit sequences are allocated into N orthogonal…
Non-volatile memory with source line resistance compensation
Granted: April 20, 2021
Patent Number:
10984872
A non-volatile memory device determines the bit-line location of a memory cell selected for memory operation relative to a nearest source line, generates a modified bit-line bias voltage based on the bit-line location and applies the modified bit-line bias voltage to the selected memory cell. In some embodiments, the memory cell is selected to be programmed. In this manner, the non-volatile memory device compensates for source line resistance at the memory cells.
Wide range output driver circuit for semiconductor device
Granted: February 2, 2021
Patent Number:
10911044
An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal.…
Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
Granted: November 10, 2020
Patent Number:
10832747
A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having…
PVT-independent fixed delay circuit
Granted: November 3, 2020
Patent Number:
10826473
A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.
Repetition scheme for flexible bandwidth utilization
Granted: March 10, 2020
Patent Number:
10587365
A network device implements a repetition scheme to generate a repetition-encoded FEC codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of bit sequences concatenated together. The set of bit sequences corresponds to a set of OFDM symbols. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. In one embodiment, a right cyclic…
Domain establishment, registration and resignation via a push button mechanism
Granted: October 8, 2019
Patent Number:
10439674
A network node includes a pushbutton to provide a button-press event and a pairer to receive the button-press event while not being in a secure domain. In response to the button-press, the pairer alternates between acting as an endpoint node and acting as a temporary domain master, until pairing is completed. In an alternative embodiment, the node includes a multi-pairer to receive the button press event and, in response, to open a pairing window, to become a domain master of a secure…
Embedded transconductance test circuit and method for flash memory cells
Granted: October 1, 2019
Patent Number:
10431321
A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.
Secured chip enable with chip disable
Granted: June 25, 2019
Patent Number:
10331575
A memory device incorporates a chip enable protection circuit implementing a secured chip enable method providing a passcode protected enable scheme with secure chip disable for the memory device. The passcode can be programmed at manufacturing or programmed by the user. Memory device access is enabled by receiving the correct passcode and memory device access is denied when the wrong passcode is entered. Furthermore, the secured chip enable method implements secure chip disable where…
Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
Granted: March 19, 2019
Patent Number:
10236042
A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having…
Memory device read training method
Granted: March 12, 2019
Patent Number:
10229743
A memory device implements a memory read training method using a dedicated read command to retrieve training data from a register for performing memory read training while the memory device remains operating in the normal operation mode. Subsequent to the memory read training, the memory device may then receive the normal read command to read data from the memory cell array or the normal write command to write data to the memory cell array. In this manner, memory read training is…
