Dual match-line, twin-cell, binary-ternary CAM
Granted: March 9, 2004
Patent Number:
6704216
A content addressable memory (CAM)(10, 102) and method having a data-in sub-circuit (44), memory cells (16, 18), a match-high line (36), a match-low line (38), and pre-charge devices (40, 42). Input lines (30, 32, 48, 50) from the data-in sub-circuit (44) are not necessarily discharged to ground in every cycle of a clock signal (62) used by the memory cells (16, 18). Further, the pre-charge devices (40, 42) may be operated at one half of the rate of the clock signal (62). Yet further,…
Paralleled content addressable memory search engine
Granted: September 30, 2003
Patent Number:
6629099
A parallel search engine able to receive commands via a search instruction input and data words via a search data input. The commands received, which are optionally programmable, control operation of a data dispatch unit and a result dispatch unit. The data words received are sent by the data dispatch unit as search data to a CAM module array made up of CAM modules interconnected by a cascade information bus for comparison against pre-stored comparand databases. The CAM modules of the…
System and method for combining integrated circuit final test and marking
Granted: May 28, 2002
Patent Number:
6396295
A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.
Pulse delay circuit with stable delay
Granted: March 5, 2002
Patent Number:
6353349
A pulse delay circuit that provides a delay for a pulsed input signal that does not vary significantly under changing temperature, power supply voltage or process conditions. The delay provided by the pulse delay circuit is not significantly limited in duration. The pulse delay circuit includes a pulse detector, an RC delay circuit and a pulsed signal generator. The delay is primarily determined by the RC time constant of the RC delay circuit.
Method for fabricating stacked capacitor for a dynamic random access memory
Granted: February 6, 2001
Patent Number:
6184152
A method is provided for fabricating an array of memory cells for a dynamic random access memory. Each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, a drain and a gate. The source is coupled to a bit line, and the gate is coupled to a word line. A lower conductive layer is formed over the array of memory cell transistors. The lower conductive layer is electrically coupled to the source of the memory…
Insertble and removable digital memory apparatus
Granted: January 16, 2001
Patent Number:
6175517
Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor…
Apparatus and method for preventing accidental writes from occurring due to simultaneous address and write enable transitions
Granted: August 8, 2000
Patent Number:
6101133
A Random Access Memory (RAM) with improved memory access time supporting simultaneous transitions of an address signal and a write enable signal while preventing accidental writes. The RAM includes a memory array, an address transition detector and a race detector. Operation of the memory array is controlled by the address signal and a write clock signal. In response to the write clock's read state the memory array reads data from an address represented by the address signal, while the…
High density self-aligned antifuse
Granted: July 11, 2000
Patent Number:
6087677
The present invention is an antifuse structure comprising an insulation layer between a top conductor and a bottom conductor. The insulation layer has a via. A resistive layer is adjacent the via and a plug is adjacent the resistive layer. The plug is in the via and is also adjacent the top conductor.The present invention also provides a method for fabricating the antifuse on a base. A bottom conductor is deposited on the base. An insulation layer are deposited adjacent the bottom…
Self-aligned storage node definition in a DRAM that exceeds the photolithography limit
Granted: June 13, 2000
Patent Number:
6074910
A method is provided for fabricating a stacked capacitor in a storage node (memory cell) of a dynamic random access memory (DRAM) that exceeds the photolithography limit. A DRAM has an array of memory cells and each memory cell has an associated capacitor. An array of memory cell transistors is formed and each memory cell transistor has a source, drain and gate. The drain is coupled to a bit line, and the gate coupled to a word line. A lower conductive layer is formed over the array of…
Leakage improved charge pump for nonvolatile memory device
Granted: May 30, 2000
Patent Number:
6069519
A distribution charge pump is disclosed that reduces leakage from a VPP node where a programming voltage (VPP) is provided. The distribution charge pump includes a pump section and a biasing network. The pump section, in response to input signals at 0V or VCC, generates corresponding output signals at 0V or VPP, respectively. Typically, VCC can be between 2V and 5V and VPP can be between 11V and 15V. The pump section includes two n-channel transistors that bootstrap each other to…
System and method for a low voltage charge pump with large output voltage range
Granted: May 16, 2000
Patent Number:
6064251
A low voltage charge pump system with a large output voltage range is described. The charge pump system comprises eight charge pump stages, an output stage, and a four phase clock generator. The clock generator generates two sets of four phase shifted signals. The first set of four clock signals are coupled to the first four charge pump stages and have a logic high level of VCC. The second set of clock signals are coupled to the second four charge pump stages and have a logic high level…
DRAM repair apparatus and method
Granted: April 4, 2000
Patent Number:
6046945
An apparatus and method for minimizing the access time incurred when accessing redundant columns of a dynamic random access memory (DRAM) is herein disclosed. A pair of redundant columns is associated with a defective column. Each pair of redundant columns has a single redundant column decoder that provides access to the column data in the pair of redundant columns. The redundant column decoder is enabled by the column repair circuitry when it receives a column address signal indicating…
Fast on-chip current measurement circuit and method for use with memory array circuits
Granted: February 29, 2000
Patent Number:
6031777
A high speed memory cell current measurement circuit uses an on-chip reference current circuit that generates a reference current Iref. The reference current circuit includes a first current source transistor. An on-chip current comparison circuit has a second current source transistor that is coupled to the first current source transistor so as to mirror the reference current Iref at a fixed current ratio WR. The current comparison circuit has a current connection path connecting the…
Guaranteed dynamic pulse generator
Granted: February 22, 2000
Patent Number:
6028814
The present invention is dynamic pulse generator for generating an output pulse from a first input pulse and a second input pulse, where the output pulse is guaranteed to have a pulse width of at least the pulse width of whichever of the two input pulses has a delayed leading edge with respect to the other. The first input pulse has a first leading edge and a first trailing edge. The second input pulse has a second leading edge and a second trailing edge. The second leading edge is…
Insertable and removable high capacity digital memory apparatus and methods of operation thereof
Granted: February 15, 2000
Patent Number:
6026007
Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor…
Multiple row address strobe DRAM architecture to improve bandwidth
Granted: February 15, 2000
Patent Number:
6026466
A multibank DRAM memory is described having individual row address strobe bar (RASB) and column address strobe bar (CASB) signals. Logically, only one row can be activated in each memory bank at a time and column access can be performed on one memory bank at a time. A token state machine is used to coordinate column access. In a first embodiment, two banks are utilized having respective asynchronous RASB signals transmitted from an external source. In a second embodiment, N DRAM memory…
Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations
Granted: December 21, 1999
Patent Number:
6005810
A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and…
Smart five volt generator operable from different power supply voltages
Granted: December 14, 1999
Patent Number:
6002604
A 5V generator circuit is disclosed that generates a reliable 5V signal for use in integrated circuits from the available VPP or VCC supplies for a wide range of VPP and VCC voltages. When VCC is greater than approximately 4V, the generator circuit generates the 5V signal directly from VCC. When VCC is less than approximately 4V and VPP is greater than approximately 4V but less than about 9V, the generator circuit generates the 5V signal directly from VPP. When VCC is less than…
Row decoder for nonvolatile memory having a low-voltage power supply
Granted: December 7, 1999
Patent Number:
5999479
A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.
Charge pump system with improved programming current distribution
Granted: November 9, 1999
Patent Number:
5982223
A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2…
