Flash memory array having well contact structures
Granted: October 26, 1999
Patent Number:
5973374
A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the…
Voltage regulator for a voltage pump in a DRAM
Granted: September 21, 1999
Patent Number:
5955914
The Vpp generator for use in a dynamic random access memory has a pump circuit and a voltage regulator. The voltage regulator controls the pump circuit such that the pumped up voltage has a maximum predetermined value. The prior art Vpp regulator sets the pumped up voltage, Vpp, to approximately a supply voltage, Vcc, plus the threshold voltage of a memory cell access transistor. This level becomes very high when the supply voltage, Vcc, is high and may overstress the devices. The…
Apparatus and method for minimizing address hold time in asynchronous SRAM
Granted: August 24, 1999
Patent Number:
5943288
A write control circuit and method for an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory. The write control circuit temporarily disables a write circuit in the memory whenever the memory address changes. The delay of the write control circuit from input to output is shorter than the delay of a decoder in the memory.
Method and apparatus for controlling memory address hold time
Granted: August 17, 1999
Patent Number:
5940337
A self timed memory address control circuit is described. A Y address signal is pre-decoded and then latched. Address transition detection circuits coupled to X and Y address lines output a pulse to an equalization circuit whenever one of the corresponding address signals change. The WEB address detection circuit outputs a pulse when the WEB signal switches high. When the equalization circuit receives one of these pulses it generates an output pulse to an equalization transistor that is…
System and method for a flexible memory controller
Granted: August 3, 1999
Patent Number:
5933385
A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without…
Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes
Granted: March 30, 1999
Patent Number:
5888894
A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form…
Method and apparatus for operating functions relating to memory and/or applications that employ memory in accordance with available power
Granted: March 30, 1999
Patent Number:
5889721
A programmable memory device includes circuits that permit the selective disabling of certain functions when a battery supply voltage falls below the point necessary to sustain those functions while not disabling other functions of the device capable of working at the lower supply voltage. The programmable memory device includes a controller (422), programmable memory (426), and a voltage monitor (424), and is used in an application having additional circuitry (430). Power is furnished…
High voltage charge transfer stage
Granted: March 23, 1999
Patent Number:
5886566
An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock…
Local row decoder for sector-erase fowler-nordheim tunneling based flash memory
Granted: March 23, 1999
Patent Number:
5886923
A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling, local decoder circuitry. The local decoder includes a set of word line drivers, each of which sets the voltage level of a corresponding local word…
Non-volatile programmable memory having a buffering capability and method of operation thereof
Granted: January 19, 1999
Patent Number:
5862099
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming…
Fuse tunable, RC-generated pulse generator
Granted: December 22, 1998
Patent Number:
5852379
A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driven by a clock signal and generates therefrom a self-resettable output signal pulse with a selectable pulse width no longer than the width of the clock signal. The variable widths are provided…
Address enable circuit in synchronous SRAM
Granted: December 8, 1998
Patent Number:
5848022
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not…
Driver circuit for use with a sensing amplifier in a memory
Granted: December 1, 1998
Patent Number:
5844428
A novel driver circuit is disclosed that is used for driving a logic voltage sensed by a sensing amplifier of a memory onto a data line of the memory. The driver circuit is responsive to first sensing signals and second sensing signals that are delayed with respect to the first sensing signals. When the first and second sensing signals indicate that equalization is occuring in the sensing amplifier, the driver circuit latches the data line logic voltage on the data line without any false…
Drain voltage pump circuit for nonvolatile memory device
Granted: October 6, 1998
Patent Number:
5818766
A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose…
System and method for a high speed, high voltage latch for memory devices
Granted: September 22, 1998
Patent Number:
5812463
The present invention provides a high speed, high voltage latch that minimizes leakage current and vulnerability to latch-up. The latch has a switching transistor between a program power supply and the output. The switching transistor is turned off by the latch input when the latch input transitions so as drive the output to a low level. The switching transistor thereby minimizes leakage current. An output driver transistor coupled to the program power supply is used. The latch output is…
Wordline wakeup circuit for use in a pulsed wordline design
Granted: September 22, 1998
Patent Number:
5812482
A wordline wakeup circuit for use in a static memory responsive to an external clock signal and chip enable signals provided by a controller/microprocessor to perform a memory operation on the static memory. The wordline wakeup circuit receives a global clock (GCLK) signal generated by memory control circuitry from the external clock signal and a word line enable (WLEN) signal asserted by the control circuitry when the chip enables indicate a pending memory operation. The wordline wakeup…
Multiple location repair word line redundancy circuit
Granted: June 30, 1998
Patent Number:
5774471
A multi-location word line repair circuit is described that can be employed in a static memory including a plurality of sub-arrays responsive to respective sets of global word lines (GWL). Included in the repair circuit is a redundant word line (WL) decoder that stores and subsequently decodes the address of a defective global word line to be repaired. A selector circuit coupled to the redundant WL decoder is activated whenever the decoder decodes the stored address of the defective GWL…
Distribution charge pump for nonvolatile memory device
Granted: June 16, 1998
Patent Number:
5767729
A distribution charge pump is disclosed that provides a high voltage output that can be used to write or erase EEPROM cells. The charge pump is enabled by a high (VCC) input signal, which is input to a pair of always-on pass transistors. The output of one of these pass transistors turns on a third transistor whose source is tied to an internal node that is coupled to one terminal of a MOS capacitor and the gate of a fourth transistor. The other terminal of the MOS capacitor is tied to a…
Space efficient column decoder for flash memory redundant columns
Granted: March 17, 1998
Patent Number:
5729551
The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The…
On-chip positive and negative high voltage wordline x-decoding for EPROM/FLASH
Granted: August 26, 1997
Patent Number:
5661683
An on-chip positive and negative high voltage wordline x-decoding system for EPROM/FLASH is disclosed wherein three transistors are required for each wordline. The x-decoding system minimizes system latch-up by separating the positive and negative high voltage portions of the system. The high-voltage portion of the x-decoding system includes a native mode PMOS transistor fabricated in a N-well on a common P-substrate and a high-voltage NAND gate that supplies a control signal to the gate…
