Multiple row address strobe DRAM architecture to improve bandwidth
Granted: February 15, 2000
Patent Number:
6026466
A multibank DRAM memory is described having individual row address strobe bar (RASB) and column address strobe bar (CASB) signals. Logically, only one row can be activated in each memory bank at a time and column access can be performed on one memory bank at a time. A token state machine is used to coordinate column access. In a first embodiment, two banks are utilized having respective asynchronous RASB signals transmitted from an external source. In a second embodiment, N DRAM memory…
Insertable and removable high capacity digital memory apparatus and methods of operation thereof
Granted: February 15, 2000
Patent Number:
6026007
Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor…
Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations
Granted: December 21, 1999
Patent Number:
6005810
A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and…
Smart five volt generator operable from different power supply voltages
Granted: December 14, 1999
Patent Number:
6002604
A 5V generator circuit is disclosed that generates a reliable 5V signal for use in integrated circuits from the available VPP or VCC supplies for a wide range of VPP and VCC voltages. When VCC is greater than approximately 4V, the generator circuit generates the 5V signal directly from VCC. When VCC is less than approximately 4V and VPP is greater than approximately 4V but less than about 9V, the generator circuit generates the 5V signal directly from VPP. When VCC is less than…
Row decoder for nonvolatile memory having a low-voltage power supply
Granted: December 7, 1999
Patent Number:
5999479
A row decoder for a nonvolatile memory having a low-voltage power supply that minimizes the load capacitance presented to a high voltage source without requiring additional circuitry. The row decoder accomplishes this by providing a local decoder having only one input requiring a boosted voltage higher than the power supply voltage. Further, predecoders are used to reduce the number of local decoders that receive the boosted voltage.
Charge pump system with improved programming current distribution
Granted: November 9, 1999
Patent Number:
5982223
A voltage pump circuit includes a native MOS device coupled as a charge transfer device (M1) between input and output stage nodes. A parallel-coupled MOS pair (M2, M3) is coupled between drain (input node) and source (output node) of the charge transfer device, in which M3 is configured as a diode. A clock generator outputs at least three non-overlapping phase signals: .phi.1 (which goes high at t1 and low at t6), .phi.2 (which goes high at t3 and low at t4), .phi.3 (which goes low qt t2…
Flash memory array having well contact structures
Granted: October 26, 1999
Patent Number:
5973374
A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the…
Voltage regulator for a voltage pump in a DRAM
Granted: September 21, 1999
Patent Number:
5955914
The Vpp generator for use in a dynamic random access memory has a pump circuit and a voltage regulator. The voltage regulator controls the pump circuit such that the pumped up voltage has a maximum predetermined value. The prior art Vpp regulator sets the pumped up voltage, Vpp, to approximately a supply voltage, Vcc, plus the threshold voltage of a memory cell access transistor. This level becomes very high when the supply voltage, Vcc, is high and may overstress the devices. The…
Apparatus and method for minimizing address hold time in asynchronous SRAM
Granted: August 24, 1999
Patent Number:
5943288
A write control circuit and method for an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory. The write control circuit temporarily disables a write circuit in the memory whenever the memory address changes. The delay of the write control circuit from input to output is shorter than the delay of a decoder in the memory.
Method and apparatus for controlling memory address hold time
Granted: August 17, 1999
Patent Number:
5940337
A self timed memory address control circuit is described. A Y address signal is pre-decoded and then latched. Address transition detection circuits coupled to X and Y address lines output a pulse to an equalization circuit whenever one of the corresponding address signals change. The WEB address detection circuit outputs a pulse when the WEB signal switches high. When the equalization circuit receives one of these pulses it generates an output pulse to an equalization transistor that is…
System and method for a flexible memory controller
Granted: August 3, 1999
Patent Number:
5933385
A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without…
Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes
Granted: March 30, 1999
Patent Number:
5888894
A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form…
Method and apparatus for operating functions relating to memory and/or applications that employ memory in accordance with available power
Granted: March 30, 1999
Patent Number:
5889721
A programmable memory device includes circuits that permit the selective disabling of certain functions when a battery supply voltage falls below the point necessary to sustain those functions while not disabling other functions of the device capable of working at the lower supply voltage. The programmable memory device includes a controller (422), programmable memory (426), and a voltage monitor (424), and is used in an application having additional circuitry (430). Power is furnished…
High voltage charge transfer stage
Granted: March 23, 1999
Patent Number:
5886566
An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock…
Local row decoder for sector-erase fowler-nordheim tunneling based flash memory
Granted: March 23, 1999
Patent Number:
5886923
A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling, local decoder circuitry. The local decoder includes a set of word line drivers, each of which sets the voltage level of a corresponding local word…
Non-volatile programmable memory having a buffering capability and method of operation thereof
Granted: January 19, 1999
Patent Number:
5862099
A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming…
Fuse tunable, RC-generated pulse generator
Granted: December 22, 1998
Patent Number:
5852379
A tunable phase generator is disclosed suitable for use in integrated circuits. The phase generator includes a delay element wherein passive resistors and conductors are employed to provide relatively constant delays despite changes in operating temperatures and voltages. The phase generator is driven by a clock signal and generates therefrom a self-resettable output signal pulse with a selectable pulse width no longer than the width of the clock signal. The variable widths are provided…
Address enable circuit in synchronous SRAM
Granted: December 8, 1998
Patent Number:
5848022
A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not…
Driver circuit for use with a sensing amplifier in a memory
Granted: December 1, 1998
Patent Number:
5844428
A novel driver circuit is disclosed that is used for driving a logic voltage sensed by a sensing amplifier of a memory onto a data line of the memory. The driver circuit is responsive to first sensing signals and second sensing signals that are delayed with respect to the first sensing signals. When the first and second sensing signals indicate that equalization is occuring in the sensing amplifier, the driver circuit latches the data line logic voltage on the data line without any false…
Drain voltage pump circuit for nonvolatile memory device
Granted: October 6, 1998
Patent Number:
5818766
A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose…
