System and method for a high speed, high voltage latch for memory devices
Granted: September 22, 1998
Patent Number:
5812463
The present invention provides a high speed, high voltage latch that minimizes leakage current and vulnerability to latch-up. The latch has a switching transistor between a program power supply and the output. The switching transistor is turned off by the latch input when the latch input transitions so as drive the output to a low level. The switching transistor thereby minimizes leakage current. An output driver transistor coupled to the program power supply is used. The latch output is…
Wordline wakeup circuit for use in a pulsed wordline design
Granted: September 22, 1998
Patent Number:
5812482
A wordline wakeup circuit for use in a static memory responsive to an external clock signal and chip enable signals provided by a controller/microprocessor to perform a memory operation on the static memory. The wordline wakeup circuit receives a global clock (GCLK) signal generated by memory control circuitry from the external clock signal and a word line enable (WLEN) signal asserted by the control circuitry when the chip enables indicate a pending memory operation. The wordline wakeup…
Multiple location repair word line redundancy circuit
Granted: June 30, 1998
Patent Number:
5774471
A multi-location word line repair circuit is described that can be employed in a static memory including a plurality of sub-arrays responsive to respective sets of global word lines (GWL). Included in the repair circuit is a redundant word line (WL) decoder that stores and subsequently decodes the address of a defective global word line to be repaired. A selector circuit coupled to the redundant WL decoder is activated whenever the decoder decodes the stored address of the defective GWL…
Distribution charge pump for nonvolatile memory device
Granted: June 16, 1998
Patent Number:
5767729
A distribution charge pump is disclosed that provides a high voltage output that can be used to write or erase EEPROM cells. The charge pump is enabled by a high (VCC) input signal, which is input to a pair of always-on pass transistors. The output of one of these pass transistors turns on a third transistor whose source is tied to an internal node that is coupled to one terminal of a MOS capacitor and the gate of a fourth transistor. The other terminal of the MOS capacitor is tied to a…
Space efficient column decoder for flash memory redundant columns
Granted: March 17, 1998
Patent Number:
5729551
The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The…
On-chip positive and negative high voltage wordline x-decoding for EPROM/FLASH
Granted: August 26, 1997
Patent Number:
5661683
An on-chip positive and negative high voltage wordline x-decoding system for EPROM/FLASH is disclosed wherein three transistors are required for each wordline. The x-decoding system minimizes system latch-up by separating the positive and negative high voltage portions of the system. The high-voltage portion of the x-decoding system includes a native mode PMOS transistor fabricated in a N-well on a common P-substrate and a high-voltage NAND gate that supplies a control signal to the gate…
System and method for controlling source current and voltage during flash memory erase operations
Granted: June 24, 1997
Patent Number:
5642310
A double erase control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. A host selectively erases flash memory cells by placing 0 VDC on the word lines and a large positive voltage (10.4 VDC to 10.8 VDC) on an array virtual ground supply (VVSS) line while the drains of the memory cells float. The voltage and current…
Program verify and erase verify control circuit for EPROM/flash
Granted: November 26, 1996
Patent Number:
5579262
A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i.e., highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i.e., lowest) read voltage on…
Program drain voltage control for EPROM/flash
Granted: October 22, 1996
Patent Number:
5568425
A program drain voltage control system is disclosed for use within an EPROM/flash memory system wherein each memory cell is coupled in series with plural y selection transistors. When the EPROM/flash memory system is in programming mode, the control system maintains the program drain voltage of EPROM/flash memory cells being programmed at a target drain voltage (+6.1 VDC ). Drain voltage control is accomplished using a current control circuit and a voltage control circuit. The voltage…
Method of making an EEPROM
Granted: September 26, 1995
Patent Number:
5453388
Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming…
Non-volatile semiconductor memory cell
Granted: December 13, 1994
Patent Number:
5373465
Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming…
Non-volatile semiconductor memory cell
Granted: May 31, 1994
Patent Number:
5317179
Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming…
Full-featured EEPROM
Granted: June 1, 1993
Patent Number:
5216268
Disclosed is a byte-erasable EEPROM memory cell which utilizes a five volt external source and a voltage multiplier circuit to program and erase a floating gate by means of electron tunneling. To prevent collapse of the voltage multiplier circuit a lightly doped drain region is incorporated preventing gate modulated junction breakdown, thereby preventing collapse of the voltage multiplier circuit. In addition, current flow through the channel separating a source region and the lightly…
