COMPRESSION TECHNIQUES
Granted: December 5, 2024
Application Number:
20240403259
Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.
HYBRID AND ADAPTIVE COOLING MECHANISMS
Granted: December 5, 2024
Application Number:
20240407142
Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and…
COVERS FOR INTEGRATED CIRCUIT PACKAGE SOCKETS
Granted: December 5, 2024
Application Number:
20240407092
Covers for integrated circuit package sockets are disclosed herein. An example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.
METHOD AND SYSTEM OF AUTOMATIC MICROPHONE SELECTION FOR MULTI-MICROPHONE ENVIRONMENTS
Granted: December 5, 2024
Application Number:
20240406622
A computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. The audio signals are associated with audio emitted from a same source. The method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.
EFFICIENT MERGE CANDIDATE RANKING AND SELECTION IN VIDEO ENCODING
Granted: December 5, 2024
Application Number:
20240406380
A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank…
ANTENNA MODULES AND COMMUNICATION DEVICES
Granted: December 5, 2024
Application Number:
20240405433
Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna…
INTEGRATED CIRCUIT DEVICES WITH FISHBONE CAPACITOR STRUCTURES
Granted: December 5, 2024
Application Number:
20240404943
Disclosed herein are IC devices with fishbone capacitor structures. An example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a…
SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
Granted: December 5, 2024
Application Number:
20240404917
Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner…
MACHINE LEARNING ACCELERATOR MECHANISM
Granted: December 5, 2024
Application Number:
20240403620
An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.
CONTENT SUMMARIZATION AND/OR RECOMMENDATION APPARATUS AND METHOD
Granted: December 5, 2024
Application Number:
20240403376
Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated…
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC
Granted: December 5, 2024
Application Number:
20240403044
Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which…
GESTURE INPUT WITH MULTIPLE VIEWS, DISPLAYS AND PHYSICS
Granted: December 5, 2024
Application Number:
20240402828
Gesture input with multiple displays, views, and physics is described. In one example, a method includes generating a three dimensional space having a plurality of objects in different positions relative to a user and a virtual object to be manipulated by the user, presenting, on a display, a displayed area having at least a portion of the plurality of different objects, detecting an air gesture of the user against the virtual object, the virtual object being outside the displayed area,…
KINEMATICALLY ALIGNED OPTICAL CONNECTOR FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
Granted: December 5, 2024
Application Number:
20240402443
A kinematically aligned optical connector may be implemented with a silicon PIC component and a glass substrate component. The kinematically aligned optical connector includes one or more kinematic connectors or mechanical alignment features and visual fiducials that enable true kinematic coupling (i.e., in a three-dimensional Cartesian coordinate system, full constraint in all 6 degrees of freedom, meaning, X, Y, Z planes and all 3 angles), and enables an increased thickness of the…
PHOTONIC INTEGRATED CIRCUIT EDGE COUPLING AND FIBER ATTACH UNIT ATTACHMENT STRESS RELIEF
Granted: December 5, 2024
Application Number:
20240402442
The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A…
UNIFIED PROGRAMMING INTERFACE FOR REGRAINED TILE EXECUTION
Granted: November 28, 2024
Application Number:
20240394119
Systems, apparatuses and methods may provide for technology that detects a tensor operation in an application, wherein the tensor operation has an unspecified tensor input size, determines the input tensor size at runtime, and selects a partition configuration for the tensor operation based at least in part on the input tensor size and one or more runtime conditions. In one example, the technology searches a lookup table for the input tensor size and at least one of the runtime…
OFFSET VOIDING SCHEME FOR VERTICAL INTERCONNECTS
Granted: November 28, 2024
Application Number:
20240397610
An integrated circuit (IC) package includes a via extending through a stack of antipads in a stack of layers, and the stack of antipads has an antipad with a shorter diameter between antipads with longer diameters. The via may have first and second connections and first and second pads at or over and under the antipads. The longer diameters (over and under the shorter diameter) may be equal. Intervening antipads of intermediate size may be between the smallest antipads and the largest…
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH LOW-LEAKAGE FOR LARGE VOLTAGE SWING OF NEGATIVE CURRENT
Granted: November 28, 2024
Application Number:
20240395800
An electrostatic discharge protection circuit, device, system, and apparatus has low-leakage for a large voltage swing of negative current.
HEAT DISSIPATION SOLUTIONS FOR INTEGRATED CIRCUIT PACKAGES
Granted: November 28, 2024
Application Number:
20240395655
In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on…
SELECTIVE UNDERFILLING USING PRE-APPLIED THERMOSET ADHESIVE
Granted: November 28, 2024
Application Number:
20240395567
Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.
CONTENT SUMMARIZATION AND/OR RECOMMENDATION APPARATUS AND METHOD
Granted: November 28, 2024
Application Number:
20240394316
Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated…
