COARSE AND FINE FILTERING FOR GPU HARDWARE-BASED PERFORMANCE MONITORING
Granted: December 19, 2024
Application Number:
20240420274
Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment,…
SCALABLE MANAGEMENT SYSTEM FOR EQUITABLE PRIORITIZED CHANNEL ACCESS IN CONTENTION-BASED NETWORKS
Granted: December 19, 2024
Application Number:
20240422819
This disclosure describes systems, methods, and devices related to prioritized access. A device may broadcast advertisements to stations (STAs) indicating specific service periods for prioritized channel access within a Basic Service Set (BSS). The device may send an indication to the STAs queued for prioritized access to transmit reservation signals at a predetermined time post a start of a contention period. The device may send contention window (CW) parameter settings to the STAs to…
DEVICE, METHOD AND SYSTEM FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION
Granted: December 19, 2024
Application Number:
20240421591
Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in…
THREE-DIMENSIONAL INTERLOCKED CORRUGATED CAPACITOR STRUCTURES
Granted: December 19, 2024
Application Number:
20240421181
Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a…
DEVICE, METHOD AND SYSTEM FOR SELECTIVELY DISABLING A POWER CLAMP CIRCUIT
Granted: December 19, 2024
Application Number:
20240421150
Techniques and mechanisms for selectively disabling functionality of a power clamp circuit which is to mitigate damage due to electrostatic discharge (ESD). In an embodiment, a shut-off circuit is coupled to receive a control signal which indicates an actual or expected future power state transition of a load. The power clamp circuit comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive…
SUBSTRATES INCLUDING MICRO-STRUCTURED THIN FILM CAPACITORS
Granted: December 19, 2024
Application Number:
20240421144
Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first…
MICROELECTRONIC ASSEMBLIES INCLUDING A MOLD MATERIAL WITH A STRESS-RELIEF TRENCH
Granted: December 19, 2024
Application Number:
20240421102
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a first die having a first surface, an opposing second surface, and a first footprint; a second die electrically coupled to the second surface of the first die and having a second footprint, wherein the second footprint is smaller than the first footprint; and a mold material on the second surface of the first die and surrounding the…
INTEGRATED CIRCUIT DEVICE WITH VERTICAL VIA PIN
Granted: December 19, 2024
Application Number:
20240421042
An IC device (e.g., a standard cell) may have one or more vertical via pins for power supply or signal transmission. The IC device may also include semiconductor structures stacked over each other along the vertical axis of the IC device and electrodes stacked over each other along the horizontal axis. An electrode may be a gate electrode over a channel region of a transistor or a trench electrode over a source region or drain region of a transistor. A vertical via pin may be connected…
INTEGRATED CIRCUIT DEVICE WITH MULTI-LENGTH GATE ELECTRODE
Granted: December 19, 2024
Application Number:
20240421002
An IC device includes a gate electrode having multiple lengths. The length of a first portion of the gate electrode, which is over a channel region in a semiconductor structure, may be longer (e.g., about 0.5-3 nm longer) than the length of a second portion of the gate electrode, which is over a channel region in another semiconductor structure. The pitches at the two portions of the gate electrode may be the same or substantially similar. The lengths of the gate electrode can be…
METHODS AND APPARATUS TO DETECT ANOMALIES IN VIDEO DATA
Granted: December 19, 2024
Application Number:
20240420468
Methods and apparatus to detect anomalies in video data are disclosed. An example apparatus disclosed herein generates a reconstructed feature vector corresponding to an input feature vector representative of a video segment, the reconstructed feature vector based on a transformation applied to the input feature vector and an inverse of the transformation applied to an output of the transformation, the input feature vector and the reconstructed feature vector including features…
SCHEDULING CONFIGURATION FOR DEEP LEARNING NETWORKS
Granted: December 19, 2024
Application Number:
20240419956
In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
CONFIGURABLE PROCESSING RESOURCE EVENT FILTER FOR GPU HARDWARE-BASED PERFORMANCE MONITORING
Granted: December 19, 2024
Application Number:
20240419447
Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment,…
RADAR APPARATUS, SYSTEM, AND METHOD
Granted: December 19, 2024
Application Number:
20240418825
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, and a plurality of Receive (Rx) antennas to receive radar Rx signals. For example, the radar Rx signals may be based on the radar Tx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the…
IMPELLER ARCHITECTURE FOR COOLING FAN NOISE REDUCTION
Granted: December 12, 2024
Application Number:
20240410396
Impeller architecture for a cooling fan and methodology for making same. The impeller architecture includes a plurality of blades, individual ones of the blades have a first end that is attached to a hub component in a sequential order, such that sequential first ends are attached to the circumference. An indexing function is applied to the sequential order, and blades or the spaces therebetween are modified accordingly to have a blade type based on their sequential location and the…
ENHANCED LOADING OF MACHINE LEARNING MODELS IN WIRELESS COMMUNICATIONS
Granted: December 12, 2024
Application Number:
20240414067
This disclosure describes systems, methods, and devices for deploying machine learning (ML) models for wireless communications. A Management Service (MnS) Producer apparatus a may include processing circuitry coupled to storage for storing information associated with deploying machine learning (ML) models, the processing circuitry configured to: receive an ML model loading request, or identify an ML model loading policy, defining an ML model and a target inference function to which the…
TWO-TERMINAL INTEGRATED CIRCUIT DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION
Granted: December 12, 2024
Application Number:
20240413147
A two-terminal IC device may be used for ESD protection. The IC device may include a deep N-well may be between a P-type substrate and a group of wells that includes a first P-well, a second P-well, and a N-well. There may be another well between the second P-well and the N-well. A P-type semiconductor structure may be formed in the P-well. Two N-type semiconductor structures may be formed in the second P-well and the N-well, respectively. A contact of the P-type semiconductor structure…
INTEGRATED CIRCUIT PACKAGES WITH FLUID SPACERS TO IMPROVE PIN LOAD DISTRIBUTION
Granted: December 12, 2024
Application Number:
20240413054
Integrated circuit packages with fluid spacers to improve pin load distribution are disclosed. An example apparatus includes an integrated circuit (IC) package, a circuit board, a socket to couple the IC package and the circuit board, a backplate coupled to the circuit board, a loading assembly to provide a stack load to the IC package, and a fluid liner positioned between the circuit board and the backplate.
MULTI-MICROPHONE AUDIO SIGNAL UNIFIER AND METHODS THEREFOR
Granted: December 12, 2024
Application Number:
20240412750
A system, article, device, apparatus, and method for a multi-microphone audio signal unifier comprises receiving, by processor circuitry, an initial audio signal from one of multiple microphones arranged to provide the initial audio signal. This also includes modifying the initial audio signal comprising using at least one neural network (NN) to generate a unified audio signal that is more generic to a type of microphone than the initial audio signal.
DYNAMIC PRECISION MANAGEMENT FOR INTEGER DEEP LEARNING PRIMITIVES
Granted: December 12, 2024
Application Number:
20240412318
One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising a hardware processing unit having a dynamic precision fixed-point unit that is configurable to convert elements of a floating-point tensor to convert the floating-point tensor into a fixed-point tensor.
APPARATUS, SYSTEM AND METHOD OF COLLABORATIVE TIME OF ARRIVAL (CTOA) MEASUREMENT
Granted: December 12, 2024
Application Number:
20240411010
Some demonstrative embodiments include apparatuses systems and/or methods of Collaborative Time of Arrival (CToA). For example, an apparatus may include circuitry and logic configured to cause a CToA broadcasting wireless communication station (STA) (bSTA) to broadcast an announcement frame to announce a ranging-to-self sequence of a CToA measurement protocol; to broadcast a first ranging measurement frame of the ranging-to-self sequence subsequent to the announcement frame; to broadcast…
