Intel Patent Applications

METHOD AND SYSTEM OF COMPUTER GRAPHICS PROCESSING SYSTEM VALIDATION FOR PROCESSING OF ENCRYPTED IMAGE CONTENT

Granted: June 13, 2019
Application Number: 20190180038
Methods, articles, and systems of computer graphics processing system validation for processing of encrypted image content are disclosed herein.

GLOBAL OPTIMAL PATH DETERMINATION UTILIZING PARALLEL PROCESSING

Granted: June 13, 2019
Application Number: 20190180406
Embodiments are generally directed to global optimal path determination utilizing parallel processing. An embodiment of an apparatus includes a central processing unit (CPU); a graphical processing unit (GPU), the GPU being capable of a plurality of processing threads; and a memory to store data for a system under evaluation, the system under evaluation including a set of nodes having a first endpoint, a second endpoint, and multiple paths between the first endpoint and the second…

METHOD AND SYSTEM OF HAZE REDUCTION FOR IMAGE PROCESSING

Granted: June 13, 2019
Application Number: 20190180423
A method, system, and article are directed to haze reduction for image processing.

SOLDER RESIST LAYER STRUCTURES FOR TERMINATING DE-FEATURED COMPONENTS AND METHODS OF MAKING THE SAME

Granted: June 13, 2019
Application Number: 20190181017
A microelectronic structure may be formed comprising a microelectronic package having a plurality of interconnects and a microelectronic substrate including an upper metallization layer and a solder resist structure, wherein the solder resist structure includes a first structure which forms an electrical connection between a first interconnect of the plurality of interconnects of the microelectronic package and the upper metallization layer of the microelectronic substrate, and wherein…

GROUP III-N MATERIAL CONDUCTIVE SHIELD FOR HIGH FREQUENCY METAL INTERCONNECTS

Granted: June 13, 2019
Application Number: 20190181099
Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the…

QUBIT-DETECTOR DIE ASSEMBLIES

Granted: June 13, 2019
Application Number: 20190181256
Disclosed herein are qubit-detector die assemblies, as well as related computing devices and methods. In some embodiments, a die assembly may include: a first die having a first face and an opposing second face, wherein a plurality of active qubit devices are disposed at the first face of the first die; and a second die, mechanically coupled to the first die, having a first face and an opposing second face, wherein a plurality of quantum state detector devices are disposed at the first…

BARRIERS FOR METAL FILAMENT MEMORY DEVICES

Granted: June 13, 2019
Application Number: 20190181337
Disclosed herein are metal filament memory devices (MFMDs), and related devices and techniques. In some embodiments, an MFMD may include: an electrode including an electrochemically active metal; an electrolyte; and a barrier material disposed between the electrode and the electrolyte, wherein the barrier material has a lower work function than the electrode.

FLEXIBLE TRANSMITTER CIRCUITRY FOR INTEGRATED CIRCUITS

Granted: June 13, 2019
Application Number: 20190181865
A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a…

DOWNLINK CONTROL CHANNEL DESIGN FOR BEAMFORMING SYSTEMS

Granted: June 13, 2019
Application Number: 20190182009
Described is an apparatus of a first User Equipment (UE) operable to communicate with on a wireless network. The apparatus may comprise a first circuitry, and a second circuitry. The first circuitry may be operable to establish a parameter set defining 5G Physical Downlink Control Channel (xPDCCH) transmission to the UE. The second circuitry may be operable to generate, for transmission to the UE, one or more messages including the parameter set.

FAST CONGESTION RESPONSE

Granted: June 13, 2019
Application Number: 20190182161
There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption…

COGNITIVE EDGE PROCESSING FOR INTERNET-OF-THINGS NETWORKS

Granted: June 13, 2019
Application Number: 20190182333
In one embodiment, an apparatus comprises circuitry, wherein the circuitry is configured to: transmit, via a communications network, first context information of a first edge device to one or more second edge devices, wherein the first context information identifies an operating environment of the first edge device based on information from one or more sensors; receive, via the communications network, second context information of the one or more second edge devices, wherein the second…

METHOD AND SYSTEM FOR FAST CHANNEL SCAN FOR DOCSIS CABLE MODEM

Granted: June 13, 2019
Application Number: 20190182532
The disclosure generally relates to a method and system for fast channel scan for DOCSIS cable modems. The disclosed exemplary embodiments are directed to hybrid fiber coaxial (HFC) modems and may be equally applied to other type of modems both wired and wireless. The disclosed embodiments enable locating the Physical Link Layer Chanel (PLC) quickly by using a beacon channel at a designated frequency offset from the PLC.

BEAM MEASUREMENT AND REPORTING IN CELLULAR NETWORKS

Granted: June 13, 2019
Application Number: 20190182696
New radio (NR), also known as fifth generation (5G) radio or fifth generation long term evolution (5G LTE)) uses a measurement gap that allows for measurement on different beams, multiple frame structure and inter-radio access technology measurement. For example, in measurement on the different beams, the UE (114) and eNB (304) beam sweep (i.e., change analog beam transmitter). The UE (114) can measure different beams from a fifth generation node B (gNB) and/or other RAN nodes. The…

DETERMINATION OF NUMBER OF PHYSICAL UPLINK CONTROL CHANNEL REPETITIONS FOR MACHINE TYPE COMMUNICATIONS

Granted: June 13, 2019
Application Number: 20190182824
Briefly, in accordance with one or more embodiments, an apparatus of a machine-type communication (MTC) user equipment (UE) comprises baseband processing circuitry to establish a radio resource control (RRC) connection with an evolved Node B (eNB), and process a message from the eNB indicating a number of repetitions of physical uplink control channel (PUCCH) transmissions to be used over multiple uplink subframes after the radio resource control connection is established.

OPPORTUNISTIC RESOURCE SHARING BETWEEN DEVICES

Granted: June 13, 2019
Application Number: 20190182839
Techniques for opportunistic resource sharing between mobile devices are described. A method comprises identifying a set of homogeneous device resources implemented by multiple devices based in part on resource configuration information received by a wireless transceiver, selecting a shared homogeneous device resource of one of the multiple devices to share between the multiple devices, and sending shared configuration information to identify the shared homogeneous device resource and a…

REPLACEABLE ON-PACKAGE MEMORY DEVICES

Granted: June 13, 2019
Application Number: 20190182955
Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate. The electronic device package can also include a processor mounted on the package substrate. Additionally, the electronic device package can include a memory socket mounted on the package substrate and operably coupled to the processor. The memory socket can be operable to removably couple with a memory module and facilitate electrical…

MECHANISMS FOR FPGA CHAINING AND UNIFIED FPGA VIEWS TO COMPOSED SYSTEM HOSTS

Granted: June 6, 2019
Application Number: 20190171601
Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining…

MAX POOLING IN A MATRIX PROCESSING ARCHITECTURE

Granted: June 6, 2019
Application Number: 20190171690
In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix…

SELECTING KEYPOINTS IN IMAGES USING DESCRIPTOR SCORES

Granted: June 6, 2019
Application Number: 20190171909
An example apparatus for selecting keypoints in image includes a keypoint detector to detect keypoints in a plurality of received images. The apparatus also includes a score calculator to calculate a keypoint score for each of the detected keypoints based on a descriptor score indicating descriptor invariance. The apparatus includes a keypoint selector to select keypoints based on the calculated keypoint scores. The apparatus also further includes a descriptor calculator to calculate…

IN-PACKAGE PHOTONICS INTEGRATION AND ASSEMBLY ARCHITECTURE

Granted: June 6, 2019
Application Number: 20190172821
In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die, and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one…