PACKAGE ARCHITECTURE WITH PACKAGE SUBSTRATE HAVING BLIND CAVITY WITH ROUTING ON SIDEWALLS
Granted: March 6, 2025
Application Number:
20250079266
Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is…
LIQUID IMMERSION COOLING SYSTEMS
Granted: March 6, 2025
Application Number:
20250081396
Immersion cooling systems are disclosed. An example immersion cooling system includes an immersion tank including a cooling fluid and a reservoir to contain a recirculated portion of the cooling fluid. The reservoir is separated from the immersion tank by a height to generate a liquid surface height variance between the cooling fluid in the immersion tank and the cooling fluid in the reservoir. A supply conduit is to fluidly couple the immersion tank and the reservoir. The cooling fluid…
MULTI-LINK DEVICE DATA CONTINUITY
Granted: March 6, 2025
Application Number:
20250081266
This disclosure describes systems, methods, and devices related to multi-link device (MLD) data continuity. An MLD device may set up one or more links with a station multi-link device (STA MLD), wherein the STA MLD comprises one or more logical entities defining separate station devices. The MLD device may transmit a data packet associated with a traffic identifier (TID) to the STA MLD. The MLD device may determine that the data packet was not received by the STA MLD. The MLD device may…
DATA COLLECTION TECHNIQUES FOR WIRELESS SYSTEMS
Granted: March 6, 2025
Application Number:
20250081056
Embodiments are related to a fifth generation (5G) or sixth generation (6G) wireless communications system. A method for an access node of a wireless system comprises encoding a session start request message to start a data collection session (DCS) to collect data for a machine learning (ML) model from a user equipment (UE) by a base station of a wireless system, the session start request message including UE context information, decoding a session start response message to indicate the…
AUDIO SPATIALIZATION
Granted: March 6, 2025
Application Number:
20250080941
An apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. The processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. The processor circuitry is to…
CONTINUED TIME SYNCHRONIZATION IN THE PRESENCE OF ATTACKS USING ATTACK-AWARE TWIN
Granted: March 6, 2025
Application Number:
20250080549
Techniques for an attack-aware digital twin in a time sensitive network are described. A method includes receiving time information for a network by an attack-aware digital twin (AADT), the AADT to simulate operations of a clock manager for a node in the network based on models of the clock manager, generating model clock control information to adjust a clock to a network time for the network, the model clock control information to contain a malicious time sample introduced by a time…
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AS A SOLID STATE BATTERY
Granted: March 6, 2025
Application Number:
20250079399
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the…
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE REGULATORS
Granted: March 6, 2025
Application Number:
20250079398
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the…
HYBRID BONDING INTERCONNECT (HBI) ARCHITECTURES AND METHODS FOR SCALABILITY
Granted: March 6, 2025
Application Number:
20250079392
Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.
INTEGRATED CIRCUIT DEVICES WITH BACKSIDE BIT LINES AND WORD LINES
Granted: March 6, 2025
Application Number:
20250079303
A memory device may include one or more semiconductor structures having a frontside and a backside, one or more gate electrodes, and metal layers at both the frontside and backside. A frontside metal layer may include metal lines that are used as bit lines of the memory device. A backside metal layer may include metal lines that are used as write bit lines of the memory device. A write bit line at the backside may be parallel to a bit line at the frontside. Another backside metal layer…
AUDIO-BASED DEVICE CONTEXT DETECTION
Granted: March 6, 2025
Application Number:
20250076496
Systems and methods are provided for an acoustic-based determination that a device is inside a bag, enabling a device to react early to a potential hot bag scenario before the device begins to overheat. Acoustic cues associated with the device being put in a bag can be detected, and an ultrasonic echo can be analyzed to identify characteristics of reflections from a bag material. Ambient acoustics are used as a cue for hot bag detection, and acoustic analysis can be implemented in an…
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING MICROCHANNEL
Granted: March 6, 2025
Application Number:
20250079263
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace…
METHODS AND APPARATUS FOR MULTI-ZONE TEMPERATURE CONTROL OF JET IMPINGEMENT COOLING OF INTEGRATED CIRCUIT PACKAGES
Granted: March 6, 2025
Application Number:
20250079262
Systems, apparatus, articles of manufacture, and methods for temperature control of jet impingement cooling of integrated circuit packages are disclosed. An example system includes: a first nozzle to direct a first portion of impingement fluid towards an integrated circuit package; a second nozzle to direct a second portion of the impingement fluid towards the integrated circuit package; a first flow restrictor to control a first pressure of the first portion of the impingement fluid…
TESSELLATION REDISTRIBUTION FOR REDUCING LATENCIES IN PROCESSORS
Granted: March 6, 2025
Application Number:
20250078198
An apparatus to facilitate tessellation redistribution for reducing latencies in processors is disclosed. The apparatus includes a processor to provide parallel interconnected geometry fixed-function units with separate front end and back ends, the front ends to perform patch culling and transmission and the back ends to perform patch reception from the front end and patch tessellation; provide a tessellation redistribution central engine to redistribute patches among the back ends using…
APPARATUS, METHOD, DEVICE AND MEDIUM FOR LABEL-BALANCED CALIBRATION IN POST-TRAINING QUANTIZATION OF DNN
Granted: March 6, 2025
Application Number:
20250077861
The disclosure provides an apparatus, method, device and medium for label-balanced calibration in post-training quantization of DNNs. An apparatus includes interface circuitry configured to receive a training dataset and processor circuitry coupled to the interface circuitry. The processor circuitry is configured to generate a small ground truth dataset by selecting images with a ground truth number of 1 from the training dataset; generate a calibration dataset randomly from the training…
INTEGRITY CHECK VALUE TRIPWIRES FOR SPATIAL AND TEMPORAL MEMORY SAFETY
Granted: March 6, 2025
Application Number:
20250077647
Techniques for using integrity check value tripwires for memory safety are described. In an embodiment, an apparatus includes an instruction decoder to decode one or more instructions to copy a memory region; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the one or more instructions, including detecting an integrity check value (ICV) mismatch; determining whether a granule in the memory region…
INFRASTRUCTURE AS CODE DEPLOYMENT MECHANISM
Granted: March 6, 2025
Application Number:
20250077299
A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.
METHODS AND APPARATUS TO REDUCE AN ACTION SPACE FOR WORKLOAD EXECUTION
Granted: March 6, 2025
Application Number:
20250077298
An example apparatus includes at least one programmable circuit to analyze workload runs for a plurality of combinations of enabled setting to determine a subset of the plurality of combinations that satisfy a target performance metric; run a workload for a second combination of enabled settings to generate a result, the second combination combining enabled settings from two or more of the subset of the plurality of combinations; analyze the result to determine the second combination…
DEVICE, METHOD AND SYSTEM TO SUPPORT A SYNCHRONOUS DATA FLOW WITH AN IDENTIFICATION OF AN EXECUTABLE TASK
Granted: March 6, 2025
Application Number:
20250077244
Techniques and mechanisms for identifying a next task to be executed for an application which is modeled with a synchronous data flow (SDF) graph. In an embodiment, the SDF graph comprises nodes which each represent a different respective task, wherein the nodes variously exchange, via channels, tokens which represent data for operations of the application. A manager circuit manages and provides access to schedule registers which provide state information at a node-specific level of…
INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS
Granted: March 6, 2025
Application Number:
20250077232
A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and…
