INSTRUCTION PREFIX ENCODING FOR CRYPTOGRAPHIC COMPUTING CAPABILITY DATA TYPES
Granted: May 8, 2025
Application Number:
20250148089
Techniques for instruction prefix encoding for cryptographic computing capability data types are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction including a first prefix; and cryptography circuitry to perform a cryptographic operation on data, the cryptographic operation to be based at least in part on the first prefix and a relative enumeration in a pointer to the data.
QUANTUM DOT ARRAY DEVICES WITH SHARED GATES
Granted: May 8, 2025
Application Number:
20250151355
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH VERTICAL SIDEWALLS
Granted: May 8, 2025
Application Number:
20250151318
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the…
AVAILABILITY AND UNAVAILABILITY IN CONTROL RESPONSE FRAMES
Granted: May 8, 2025
Application Number:
20250150968
This disclosure describes systems, methods, and devices related to control frames status. A device may receive a control frame from a station (STA) at a beginning of a transmission opportunity (TxOP) that includes availability and unavailability information. The device may acknowledge the availability and unavailability information of the STA based on fields within the control frame, including unavailability target start time field and unavailability duration field. The device may adjust…
SELECTIVE PACKING OF PATCHES FOR IMMERSIVE VIDEO
Granted: May 8, 2025
Application Number:
20250150569
Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is to select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is…
TECHNOLOGIES FOR TRANSPARENT FUNCTION AS A SERVICE ARBITRATION FOR EDGE SYSTEMS
Granted: May 8, 2025
Application Number:
20250150361
Network apparatus, communicatively coupled to a provider of services, that includes gateway circuitry to receive application programming interface (API) request data from a computing device that indicates a requested service. The gateway circuitry is to (1) select, based upon the API request data, at least one of the services corresponding to the requested service, and (2) generate, based upon mapping of the API request data to the at least one of the services, corresponding request data…
LOCAL DENSITY CONTROL FOR METAL CAPACITANCE REDUCTION
Granted: May 8, 2025
Application Number:
20250149459
An integrated circuit structure includes a plurality of interconnect lines and a plurality of dummy lines that are co-planar with the plurality of interconnect lines, where a ratio of line length to end-to-end spacing of the dummy lines varies inversely with a density of the interconnect lines within each of a plurality of regions. The regions are of approximately equal area within a rectangular grid array.
INTEGRATED CIRCUIT PACKAGES INCLUDING GLASS-CORED SUBSTRATES WITH SELF-ALIGNED THROUGH GLASS VIAS
Granted: May 8, 2025
Application Number:
20250149455
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on…
INTEGRATED CIRCUIT PACKAGES INCLUDING GLASS-CORED SUBSTRATES WITH SELF-ALIGNED THROUGH GLASS VIAS
Granted: May 8, 2025
Application Number:
20250149421
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a positive-type photo-imageable dielectric (PID) material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter…
PHYSICAL THERAPY ASSISTANT AS A SERVICE
Granted: May 8, 2025
Application Number:
20250149145
Physical therapy assistant-as-a-service (PTaaS) enables the automatic evaluation of a patient's performance of physical therapy exercises and the automatic provision of feedback to the patient on their exercise performance in real-time. A patient device can provide real-time patient exercise video to a PTaaS backend that performs checks prior to the patient performing the exercise (pre-checks) and checks during patient performance of the exercise (live checks). If any of the checks fail,…
MICROSERVICES ARCHITECTURE
Granted: May 8, 2025
Application Number:
20250147822
A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different…
MULTIPLE REGISTER ALLOCATION SIZES FOR GPU HARDWARE THREADS
Granted: May 8, 2025
Application Number:
20250147762
Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code…
OPTICAL TRANSCEIVER BANDWIDTH SCALING THROUGH DIRECT OPTICAL WIRE FIBER TERMINATION
Granted: May 8, 2025
Application Number:
20250147233
A wavelength multiplexing optical fiber transmitter, receiver, or transceiver where multiple emitters and/or photodetectors of different center wavelengths are coupled to a single optical fiber core terminus through multiple waveguides, which may be directly printed in free space. The optical assemblies described are suitable for optical data link applications, for example, to reduce a number of optical fibers needed for a given bandwidth or increase the bandwidth of a give number of…
INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS
Granted: May 1, 2025
Application Number:
20250142948
An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be…
DOUBLE-SIDED CONDUCTIVE VIA
Granted: May 1, 2025
Application Number:
20250140748
A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion…
PACKAGE ARCHITECTURE WITH THERMAL ENHANCEMENTS FOR VERTICALLY ORIENTED INTEGRATED CIRCUIT DIES
Granted: May 1, 2025
Application Number:
20250140741
Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD),…
INTEGRATED CIRCUIT DEVICES WITH BACKSIDE SEMICONDUCTOR STRUCTURES
Granted: May 1, 2025
Application Number:
20250140649
An IC device may include a semiconductor structure and a backside semiconductor structure over the semiconductor structure. The semiconductor structure and backside semiconductor structure may constitute the source or drain region of a transistor. The backside semiconductor structure may be closer to the backside of a substrate of the IC device than the semiconductor structure. The backside semiconductor structure may be formed at a lower temperature than the semiconductor structure. The…
STATEFUL FLOW TABLE MANAGEMENT USING PROGRAMMABLE NETWORK INTERFACE DEVICES
Granted: May 1, 2025
Application Number:
20250139040
An apparatus includes a host interface; a network interface; hardware storage to store a flow table; and programmable circuitry comprising processors to implement network interface functionality and to: implement a hash table and an age context table, wherein the hash table and the age context table are to reference flow rules maintained in the flow table; process a synchronization packet for a flow by adding a flow rule for the flow to the flow table, adding a hash entry corresponding…
TECHNOLOGIES FOR LOW POWER INDOOR AND OUTDOOR DETECTION
Granted: May 1, 2025
Application Number:
20250138491
Techniques for low power indoor/outdoor detection are disclosed. In the illustrative embodiment, an integrated sensor hub receives data from an accelerometer. The sensor hub processes the accelerometer data to determine an activity of the user. Depending on the activity of the user, the sensor hub may determine whether the compute device is indoors or outdoors or may receive data from additional sensors, such as a magnetometer, a gyroscope, or an ambient light sensor. The additional…
ORTHOGONAL COLD PLATE FOR USE IN ACTIVE LIQUID IMMERSION COOLING
Granted: April 24, 2025
Application Number:
20250133692
A cold plate comprises a plurality of fins. The individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. During operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. The coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. The first direction is substantially orthogonal to the second…
