Intel Patent Applications

CLOUD-BASED SCALE-UP SYSTEM COMPOSITION

Granted: July 18, 2024
Application Number: 20240241761
Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic…

DEEP LEARNING SOLUTION FOR VIRTUAL ROTATION OF BINAURAL AUDIO SIGNALS

Granted: July 18, 2024
Application Number: 20240244389
Techniques are provided herein for providing binaural sound signals that are virtually rotated to match head rotation, such that audio output to headphones is perceived to maintain its location relative to user when a user turns their head. In particular, techniques are presented to extract spherical location information already embedded in binaural signals to generate binaural sound signals that change to match head rotation. A deep-learning based audio regression method can use a…

REAL-TIME ADAPTIVE CORRECTION IN VIEWPORT PREDICTION FOR IMPROVED IMMERSIVE VIDEO

Granted: July 18, 2024
Application Number: 20240244172
Techniques related to viewport selection in immersive video contexts are discussed. Such techniques include generating multiple viewport predictions each for a future time interval and based on different prediction models, ranking the viewport predictions using error descriptors of the prediction models, selecting a viewport prediction for the future time intervals using the ranking, and correcting the selected viewport predictions using the error descriptors.

METHOD AND SYSTEM OF UNIFIED AUTOMATIC WHITE BALANCING FOR MULTI-IMAGE PROCESSING

Granted: July 18, 2024
Application Number: 20240244171
A method, system, and article provide unified automatic white balancing for multi-image processing.

EXTENDED LINK-TRAINING TIME NEGOTIATED ON LINK START-UP

Granted: July 18, 2024
Application Number: 20240243951
Examples described herein relate to link training between network connected devices. In some examples, an amount to extend link training is determined. The amount to extend link training can be determined by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals indicating capability to extend link training time and amount to extend link training time; determining, at the first device, a link training time based on a default…

VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES

Granted: July 18, 2024
Application Number: 20240243052
An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit…

GAME FOCUS ESTIMATION IN TEAM SPORTS FOR IMMERSIVE VIDEO

Granted: July 18, 2024
Application Number: 20240242462
Techniques related to game focus estimation in team sports for multi-camera immersive video are discussed. Such techniques include selecting regions of a scene comprising a sporting event, generating a node graph and sets of features for the selected regions, and determining a game focus region of the selected regions by applying a graph node classification model based on the node graph and sets of features.

IMMUTABLE WATERMARKING FOR AUTHENTICATING AND VERIFYING AI-GENERATED OUTPUT

Granted: July 18, 2024
Application Number: 20240242128
Embodiments are directed to immutable watermarking for authenticating and verifying artificial intelligence (AI)-generated output. An embodiment of a system includes a processor of a monitoring system, wherein the processor is to: receive first content from a first device and second content from a second device, wherein the first content comprises output of inferences of a machine learning (ML) model as applied to captured content at the first device; extracting, from a digital signature…

ACCELERATION OF NETWORK INTERFACE DEVICE TRANSACTIONS USING COMPUTE EXPRESS LINK

Granted: July 18, 2024
Application Number: 20240241847
A network interface device includes a port with protocol circuitry to couple to a host device by a link compliant with a Compute Express Link (CXL) protocol. The network interface device further includes a memory and logic to support emulation of a file system by the host device of at least a portion of the memory, where the link is used for direct memory accesses for requests or responses associated with the emulation of the file system.

NETWORK CONTROLLER LOW LATENCY DATA PATH

Granted: July 18, 2024
Application Number: 20240241843
A network controller is coupled to a memory associated with a hardware accelerator and includes a first port to couple to a host system, wherein the host system comprises system memory and a second port to receive data over a network. The network controller comprises circuitry to determine that the data is to be written directly to the memory instead of to the system memory and write the data to the memory for consumption by the hardware accelerator.

APPARATUSES, METHODS, AND SYSTEMS FOR 8-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS

Granted: July 18, 2024
Application Number: 20240241722
Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to…

MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH OPERATIONS

Granted: July 18, 2024
Application Number: 20240241693
A processor to facilitate execution of a single-precision floating point operation on an operand is disclosed. The processor includes one or more execution units, each having a plurality of floating point units to execute one or more instructions to perform the single-precision floating point operation on the operand, including performing a floating point operation on an exponent component of the operand; and performing a floating point operation on a mantissa component of the operand,…

ACOUSTIC REMOTE CONTROL INTERFACE FOR HEADSETS

Granted: July 18, 2024
Application Number: 20240241690
Techniques are provided herein for implementing headset control functions for low-end consumer-grade headsets using a firmware module implemented in the computing platform. The techniques can include a microphone mute function, a headset speaker volume function, and other headset functions. In particular, acoustic events are utilized to control headset functions. Because the headset control components are inside system firmware, the headset control module is endpoint agnostic and will…

FAN ENCLOSURE WITH ADJUSTABLE SIDE VENTING

Granted: July 18, 2024
Application Number: 20240241554
Particular embodiments described herein provide for an electronic device that can be configured to include a first heat source, a second heat source, and a fan inside a fan enclosure between the first heat source and the second heat source. The fan enclosure includes a main vent to direct air from the fan towards a heatsink and one or more side vents to direct air from the fan towards the first heat source or the second heat source.

DISAGGREGATED DIE WITH INPUT/OUTPUT (I/O) TILES

Granted: July 11, 2024
Application Number: 20240232122
Embodiments may relate to a microelectronic assembly including a substrate; a first die electrically coupled to the substrate, wherein the first die includes a first edge, a second edge, a third edge opposite the first edge, and a fourth edge opposite the second edge; and a second die electrically coupled to the substrate adjacent to the second edge of the first die and communicatively coupled to the first die, wherein the second die includes a fifth edge and a sixth edge opposite the…

PROTECTING DATA TRANSFER BETWEEN A SECURE APPLICATION AND NETWORKED DEVICES

Granted: July 11, 2024
Application Number: 20240236058
An apparatus to facilitate protecting data transfer between a secure application and networked devices is disclosed. The apparatus includes a processor to provide a trusted execution environment (TEE) to run an application, wherein the processor is to: generate, via the application in the TEE, encrypted data, wherein the encrypted data comprises a payload; copy, via the application in the TEE, the encrypted data to a local buffer; interface, using the application in the TEE, with a…

HIGH SPEED INTERCONNECT SYMBOL STREAM FORWARD ERROR-CORRECTION

Granted: July 11, 2024
Application Number: 20240235733
Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

INTEGRATED INDUCTOR OVER TRANSISTOR LAYER

Granted: July 11, 2024
Application Number: 20240234303
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE

Granted: July 11, 2024
Application Number: 20240234234
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

INCREMENTAL NEURAL REPRESENTATION FOR FAST GENERATION OF DYNAMIC FREE-VIEWPOINT VIDEOS

Granted: July 11, 2024
Application Number: 20240233062
Described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. The graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.