Intel Patent Applications

REPEATING GRAPHICS RENDER PATTERN DETECTION

Granted: December 1, 2022
Application Number: 20220382347
Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

MICROELECTRONIC ASSEMBLIES

Granted: December 1, 2022
Application Number: 20220384389
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts…

THERMAL INTERFACE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE ASSEMBLIES

Granted: December 1, 2022
Application Number: 20220384306
A thermal interface structure for facilitating heat transfer from an integrated circuit device to a heat dissipation device may be fabricated to include at least one conductive wire structure wherein each conductive wire structure includes a conductive wire having a first end, a first barrier layer adjacent the first end of the conductive wire, and a first solder structure adjacent the first barrier layer. The thermal interface structure may further include an encapsulation material…

REAL-TIME TEMPORALLY CONSISTENT OBJECT SEGMENTED STYLE TRANSFER IN MEDIA AND GAMING

Granted: December 1, 2022
Application Number: 20220383580
One embodiment provides a method comprising, at a runtime library executed by a processor of a data processing system, receiving an input frame having objects to be stylized via a style transfer network associated with the runtime library, wherein the style transfer network is a neural network model trained to apply one or more visual styles to an input frame, performing instance segmentation on the input frame to generate one or more instance masks to identify one or more objects to be…

DYNAMIC ALLOCATION OF CACHE BASED ON INSTANTANEOUS BANDWIDTH CONSUMPTION AT COMPUTING DEVICES

Granted: December 1, 2022
Application Number: 20220383447
A mechanism is described for facilitating dynamic cache allocation in computing devices in computing devices. A method of embodiments, as described herein, includes facilitating monitoring one or more bandwidth consumptions of one or more clients accessing a cache associated with a processor; computing one or more bandwidth requirements of the one or more clients based on the one or more bandwidth consumptions; and allocating one or more portions of the cache to the one or more clients…

GENERATION AND STORAGE OF COMPRESSED Z-PLANES IN GRAPHICS PROCESSING

Granted: December 1, 2022
Application Number: 20220383444
Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine…

SYNCHRONIZING OPERATION OF CONTROL CIRCUITS IN A QUANTUM CIRCUIT ASSEMBLY

Granted: December 1, 2022
Application Number: 20220383170
Systems and methods for synchronizing operation of control circuits in quantum circuit assemblies are disclosed. An example assembly for controlling operation of a qubit device includes a plurality of control circuits and an event synchronization arrangement. The plurality of control circuits may include a first and a second control circuits, configured to perform, respectively, first and second actions to control operation of the qubit device. The event synchronization arrangement may…

TECHNOLOGIES FOR EXECUTE ONLY TRANSACTIONAL MEMORY

Granted: December 1, 2022
Application Number: 20220382684
Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the…

MIXED INFERENCE USING LOW AND HIGH PRECISION

Granted: December 1, 2022
Application Number: 20220382555
One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple…

TECHNIQUES FOR DISTRIBUTED OPERATION OF SECURE CONTROLLERS

Granted: December 1, 2022
Application Number: 20220382526
Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine…

PASSIVELY ALIGNED OPTICAL INTERCONNECT COMPONENTS FOR PHOTONIC INTEGRATED CIRCUIT CHIPS

Granted: November 24, 2022
Application Number: 20220373742
Monolithic optical interconnect component components for surface mounting to photonic IC (PIC) chip assemblies. A protrusion or detent in solid body of the component comprises a contact alignment surface that stands off from a remainder of the solid body and is sloped to facilitate passive alignment of the component to a surface feature of the PIC chip. A face of the solid body may include an interference fitting to receive an MT ferrule connector. An optical interconnect component may…

APPARATUS, SYSTEM AND METHOD OF WIRELESS COMMUNICATION ACCORDING TO A HYBRID AUTOMATIC REPEAT REQUEST (HARQ) SCHEME

Granted: November 24, 2022
Application Number: 20220376841
Some demonstrative embodiments may include an apparatus including a Hybrid Automatic Repeat Request (HARQ) buffer configured to buffer compressed Log Likelihood Ratio (LLR) values corresponding to an unsuccessfully-decoded transmission of a data block, a bit size of the HARQ buffer is equal to or less than 2.5 times a supported HARQ receive (Rx) size, which is to be reported to a transmitter of the data block; and a decoder configured to decode a retransmission of the data block…

ADAPTIVE INPUT VOLTAGE SELECTION FOR A REGULATOR, CONTEXTUAL BATTERY CHARGER, AND OPTIMIZED POWER DELIVERY FOR CLAMSHELL SYSTEMS

Granted: November 24, 2022
Application Number: 20220376623
A computing system having a high-performance battery pack (e.g., 3S, 4S battery packs) coupled to a voltage regulator and logic to control an input supply of the voltage regulator. The logic determines the context of usage of the computing device (or user attentiveness) and either dynamically bypasses the voltage regulator to provide the voltage from the high-performance battery pack directly to various components of the computing system, or dynamically engages devices of the voltage…

POWER DELIVERY ARCHITECTURE FOR HIGH POWER PORTABLE DEVICES

Granted: November 24, 2022
Application Number: 20220376515
A power architecture that uses an efficient intermediate power conversion stage between AC adaptor (and battery charger) and subsequent voltage regulators (VRs) (e.g., core VR) for processors for higher overall efficiency allowing for higher performance in a given thermal envelope and iso-system input power. Power losses from both the charger and the core VR are reduced by splitting the power as power to sustained high-power rails, and power to the rest of the platform power rails that…

BARRIER AND THIN SPACER FOR 3D-NAND CUA

Granted: November 24, 2022
Application Number: 20220375946
Systems, apparatuses, and methods may provide for technology for forming a gate polysilicon for 3D-NAND complementary metal-oxide semiconductor under array (CuA) on a substrate with a barrier and spacer structure. For example, the technology includes forming a titanium nitride (TiN) barrier adjacent the gate polysilicon and forming a silicon nitride (SiN) spacer around the polysilicon gate and the titanium nitride barrier.

THREE-DIMENSIONAL MONOLITHICALLY INTEGRATED NANORIBBON-BASED MEMORY AND COMPUTE

Granted: November 24, 2022
Application Number: 20220375916
Described herein are IC devices that include multilayer memory structures bonded to compute logic using low-temperature oxide bonding to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a compute die, a multilayer memory structure, and an oxide bonding interface coupling the compute die to the multilayer memory structure. The oxide bonding interface includes metal interconnects and an oxide material surrounding the metal…

PROGRAMMABLE CAPACITANCE IN THREE-DIMENSIONAL STACKED DIE ARCHITECTURE

Granted: November 24, 2022
Application Number: 20220375898
An Integrated Circuit (IC) package is provided, comprising a first IC die having a first capacitor and a logic circuit, and a second IC die having a second capacitor. The first IC die and the second IC die may be stacked within the IC package one on top of another and electrically coupled with die-to-die interconnects. The logic circuit is electrically coupled in a power delivery network to the first capacitor and the second capacitor. The first IC die and the second IC die include…

EXTENDING ASYNCHRONOUS FRAME UPDATES WITH FULL FRAME AND PARTIAL FRAME NOTIFICATIONS

Granted: November 24, 2022
Application Number: 20220375436
Disclosed herein are techniques to provide notification of the type and/or attributes of frame updates. A platform can notify a panel of further frame updates, whether the frame update is a full frame update or a partial frame update and attributes of the frame update. The platform can notify the panel of information about the frame update during a vertical blanking interval by asserting a command or signaling the panel using selected symbols during the vertical blanking interval.

POWER OPTIMIZED TIMER MODULE FOR PROCESSORS

Granted: November 24, 2022
Application Number: 20220374065
A timer intellectual property (IP) block that automatically determines an interval on which a processor circuitry is to be woken up to service periodic events, when it is given details about the requirements for those events (e.g., approximately how often they must occur, if it's important that they not happen too frequently or too infrequently, if the total number of events over a long average is important, etc.). For each periodic event that firmware must handle, the IP provides an…

COMPUTATIONAL CURRENT SENSOR

Granted: November 24, 2022
Application Number: 20220374060
A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current…