HIGH THROUGHPUT CONTROL INFORMATION AND FIELD EXTENSION
Granted: April 10, 2025
Application Number:
20250119773
This disclosure describes systems, methods, and devices related to high throughput (HT) control information. A device may determine a frame comprising HT control information. The device may determine to extend a size of the HT control information. The device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (HT) control information, define a new control…
METHODS AND ARRANGEMENTS TO BOOST WIRELESS MEDIA QUALITY
Granted: April 10, 2025
Application Number:
20250119340
Logic may monitor quality of communication of data to a wireless receiver device based on transport characteristics at a wireless source device. Logic may evaluate the transport characteristics to identify indication(s) of a problem with the quality of the communication. Logic may identify a root cause associated with the indication(s). Logic may associate the root cause with one or more actions to mitigate the degradation of the quality. And logic may cause performance of an operation…
COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS
Granted: April 10, 2025
Application Number:
20250117874
One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network…
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
Granted: April 10, 2025
Application Number:
20250117873
Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
HIGH AVAILABILITY AI VIA A PROGRAMMABLE NETWORK INTERFACE DEVICE
Granted: April 10, 2025
Application Number:
20250117673
Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate…
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
Granted: April 10, 2025
Application Number:
20250117360
A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the…
MULTI-TILE MEMORY MANAGEMENT
Granted: April 10, 2025
Application Number:
20250117356
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second…
DEEP CAVITY METALLIZATION AND FIDUCIAL ARRANGEMENTS FOR EMBEDDED DIE AND ASSEMBLY THEREOF ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112162
An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is…
SEMICONDUCTOR DESIGN LITHOGRAPHIC SEAM IMPLEMENTATION METHODOLOGY FOR ADVANCED TECHNOLOGIES
Granted: April 3, 2025
Application Number:
20250112167
An integrated circuit (IC) device includes one or more functional blocks spanning a lithographic seam between adjacent lithographic fields. A functional block includes multiple instances of a pattern, each instance corresponding to a different placement option for the functional block. The IC device may include multiple such functional blocks spanning lithographic fields. The lithographic seam (and the patterns otherwise located) may include lithographic assist features, such as…
THROUGH-GLASS VIA LINERS FOR INTEGRATED CIRCUIT DEVICE PACKAGES
Granted: April 3, 2025
Application Number:
20250112163
An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged…
DIE EMBEDDED IN GLASS LAYER WITH TWO-SIDE CONNECTIVITY
Granted: April 3, 2025
Application Number:
20250112100
An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to…
CONFORMAL COATINGS WITH SPATIALLY DEFINED SURFACE ENERGIES FOR DIE-TO-WAFER SELF-ALIGNMENT ASSISTED ASSEMBLY
Granted: April 3, 2025
Application Number:
20250112155
Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior…
MAGNETIC AND ELECTRIC STRUCTURES IN TECHNOLOGIES WITH THROUGH-SILICON VIAS AND FRONT- AND BACK-END METAL LAYERS
Granted: April 3, 2025
Application Number:
20250112147
An integrated circuit device with front- and back-side metals may include coils in interconnect structures on one or both sides of a semiconductor substrate. The coil(s) may include vias extending through (and coupling wires on both sides of) the substrate. The coil(s) may include multiple turns or loops. The coil(s) may be on one side, and parallel to, the substrate. Coils may be orthogonal or parallel to each other. A resistor may have smaller resistor segments on both sides of the…
INTEGRATED CIRCUIT PACKAGES INCLUDING A SUBSTRATE HAVING THERMAL ISOMERIC MOIETIES AND NON-THERMAL ISOMERIC MOIETIES
Granted: April 3, 2025
Application Number:
20250112144
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); and a substrate layer on the surface of the glass layer, the substrate layer including a dielectric material, wherein the dielectric material includes an epoxy having thermal isomeric linkages, non-thermal isomeric linkages, and non-thermal isomeric epoxy…
MICROELECTRONIC STRUCTURES INCLUDING GLASS SUBSTRATES WITH DIELECTRIC BASED LINER MATERIALS.
Granted: April 3, 2025
Application Number:
20250112138
Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.
IC ASSEMBLIES WITH METAL PASSIVATION AT BOND INTERFACES
Granted: April 3, 2025
Application Number:
20250112127
A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding…
DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING
Granted: April 3, 2025
Application Number:
20250112124
DEEP CAVITY ARRANGEMENTS ON INTEGRATED CIRCUIT PACKAGING An electronic package, comprises a substrate core; dielectric material of one or more dielectric material layers over the substrate core, and having a plurality of metallization layers comprising an upper-most metallization layer; and an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer. The package also has a metallization pattern within the dielectric material and…
BACKSIDE POWER GATING
Granted: April 3, 2025
Application Number:
20250112122
Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
TECHNOLOGIES FOR DIAMOND COMPOSITE MATERIALS MANUFACTURED VIA FIELD-ASSISTED SINTERING TECHNOLOGY
Granted: April 3, 2025
Application Number:
20250112112
Technologies for diamond composite materials are disclosed. In one embodiment, field-assisted sintering technology (FAST) is used to create a diamond composite material that includes diamond particles, copper, and chromium. The chromium can help bond the copper and the diamond particles. The diamond composite material has a high thermal conductivity, such as 500-1,000 W/(m·K). In one embodiment, the diamond composite material may be used in an integrated heat spreader in an integrated…
FLEXIBLE THERMAL INTERPOSER FOR BACKSIDE COOLING OF DOUBLE-SIDED PACKAGES
Granted: April 3, 2025
Application Number:
20250112106
An integrated circuit (IC) device includes a device substrate with front- and backside IC dies and an integrated heat spreader over the backside die. The heat spreader and the backside die may be coupled to the backside of the device substrate within an array of contacts. The backside heat spreader may include a mask layer over a thermally conductive layer. The IC device may include or be coupled to second substrate (such as a motherboard). The backside heat spreader may be thermally…
