FLOATING-POINT N-INPUT SUM OF SQUARES 1ULP HARDWARE
Granted: May 2, 2024
Application Number:
20240143279
Described herein is a technique to implement an efficient floating-point n-input sum of squares operation using faithful rounding to 1 unit in the place (ULP) instead of IEEE rounding. The resulting circuitry is useful to accelerate graphics algorithms that don't require fully IEEE compliant hardware. Multipliers that are 1ulp can be significantly smaller, faster and more power efficient than IEEE rounded multipliers.
MAGNETOELECTRIC LOGIC WITH MAGNETIC TUNNEL JUNCTIONS
Granted: May 2, 2024
Application Number:
20240147867
Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor…
OPTIMIZING THE COEXISTENCE OF OPPORTUNISTIC WIRELESS ENCRYPTION AND OPEN MODE IN WIRELESS NETWORKS
Granted: May 2, 2024
Application Number:
20240147230
This disclosure describes systems, methods, and devices related to coexistence network integration. A device may transmit a beacon frame or a probe response frame containing a security element that is not a robust security network element (RSNE) element to indicate opportunistic wireless encryption (OWE) support. The device may identify a first association request frame received from a first station device (STA) comprising an RSNE element with OWE Authentication Key Management (AKM)…
MOISTURE HERMETIC GUARD RING FOR SEMICONDUCTOR ON INSULATOR DEVICES
Granted: May 2, 2024
Application Number:
20240145410
Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and…
INTEGRATED RING STRUCTURES
Granted: May 2, 2024
Application Number:
20240145383
An integrated circuit structure includes a device layer including a first set of devices and a second set of devices. An interconnect layer is above the device layer, where the interconnect layer includes one or more conductive interconnect features within dielectric material. In an example, a first ring structure including conductive material extends within the interconnect layer, and a second ring structure including conductive material extends within the interconnect layer. In an…
APPARATUS AND METHOD FOR PERFORMING NON-LOCAL MEANS FILTERING USING MOTION ESTIMATION CIRCUITRY OF A GRAPHICS PROCESSOR
Granted: May 2, 2024
Application Number:
20240144577
Apparatus and method for non-local means filtering using a media processing block of a graphics processor. For example, one embodiment of a processor comprises: ray tracing circuitry to execute a first set of one or more commands to traverse rays through a bounding volume hierarchy (BVH) to identify BVH nodes and/or primitives intersected by the ray; shader execution circuitry to execute one or more shaders responsive to a second set of one or more commands to render a sequence of image…
SALIENCY MAPS AND CONCEPT FORMATION INTENSITY FOR DIFFUSION MODELS
Granted: May 2, 2024
Application Number:
20240144447
Deep learning models, such as diffusion models, can synthesize images from noise. Diffusion models implement a complex denoising process involving many denoising operations. It can be a challenge to understand the mechanics of diffusion models. To better understand how and when structure is formed, saliency maps and concept formation intensity can be extracted from the sampling network of a diffusion model. Using the input map and the output map of a given denoising operation in a…
PROTECTION OF COMMUNICATIONS BETWEEN TRUSTED EXECUTION ENVIRONMENT AND HARDWARE ACCELERATOR UTILIZING ENHANCED END-TO-END ENCRYPTION AND INTER-CONTEXT SECURITY
Granted: May 2, 2024
Application Number:
20240143802
Embodiments are directed to protection of communications between a trusted execution environment and a hardware accelerator utilizing enhanced end-to-end encryption and inter-context security. An embodiment of an apparatus includes one or more processors having one or more trusted execution environments (TEEs) including a first TEE to include a first trusted application; an interface with a hardware accelerator, the hardware accelerator including trusted embedded software or firmware;…
TECHNOLOGIES FOR DIVIDING WORK ACROSS ACCELERATOR DEVICES
Granted: May 2, 2024
Application Number:
20240143410
Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of…
VIRTUAL MACHINE TUNNELING MECHANISM
Granted: May 2, 2024
Application Number:
20240143363
An apparatus comprising a memory device, a system on chip (SoC), including a central processing unit (CPU) to execute a virtual machine to retrieve data from the memory device and transmit the data to a remote input/output (I/O) device coupled to a remote computing platform as memory transaction data; and a port to transmit the memory transaction data as transaction layer packets (TLPs) and a network interface card (NIC) to receive the TLPs, including an interface to receive the TLPs and…
CLOCK MANAGER REDUNDANCY FOR TIME SYNCHRONIZED NETWORKS
Granted: May 2, 2024
Application Number:
20240143020
An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first…
NAMED AND CLUSTER BARRIERS
Granted: April 25, 2024
Application Number:
20240134719
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier…
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
Granted: April 25, 2024
Application Number:
20240136277
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate…
IC DIE AND HEAT SPREADERS WITH SOLDERABLE THERMAL INTERFACE STRUCTURES FOR MULTI-CHIP ASSEMBLIES INCLUDING SOLDER ARRAY THERMAL INTERCONNECTS
Granted: April 25, 2024
Application Number:
20240136244
Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder…
COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE
Granted: April 25, 2024
Application Number:
20240136243
Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.
TUNNING CONFIGURATION PARAMETERS FOR GRAPHICS PIPELINE FOR BETTER USER EXPERENCE
Granted: April 25, 2024
Application Number:
20240135485
The disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. A device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration…
INCREMENTAL NEURAL REPRESENTATION FOR FAST GENERATION OF DYNAMIC FREE-VIEWPOINT VIDEOS
Granted: April 25, 2024
Application Number:
20240135483
Described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. The graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.
DATA PRIVACY PRESERVATION IN MACHINE LEARNING TRAINING
Granted: April 25, 2024
Application Number:
20240135209
A first computing system includes a data store with a sensitive dataset. The first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. A second computing system is coupled to the first computing system and does not have access to the dataset. The second computing system uses a data synthesizer to receive the feature description data and generate a synthetic…
HARDWARE ASSISTED MEMORY ACCESS TRACKING
Granted: April 25, 2024
Application Number:
20240134803
An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.
METHODS AND APPARATUS FOR SPARSE TENSOR STORAGE FOR NEURAL NETWORK ACCELERATORS
Granted: April 25, 2024
Application Number:
20240134786
Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage…
