Intel Patent Grants

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

Granted: March 26, 2024
Patent Number: 11941169
One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated…

Apparatus, system and method of transmitting a multiple basic service set identifier (BSSID) element

Granted: March 26, 2024
Patent Number: 11943824
For example, an apparatus may be configured to generate, transmit, receive and/or process a frame including a multiple Basic Service Set Identifier (BSSID) element corresponding to a multiple BSSID set including a reporting AP, the BSSID element including one or more non-transmitted BSSID profile elements corresponding to one or more other APs belonging to the multiple BSSID set, wherein a non-transmitted BSSID profile element corresponding to an other AP includes one or more elements of…

Disaggregated computing for distributed confidential computing environment

Granted: March 26, 2024
Patent Number: 11941457
An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a source remote direct memory access (RDMA) network interface controller (RNIC); a queue to store a data entry corresponding to an RDMA request between the source RNIC and a sink RNIC; a data buffer to store data for an RDMA transfer corresponding to the RDMA request, the RDMA transfer between the source RNIC and the sink RNIC; and a trusted…

Graph partitioning to exploit batch-level parallelism

Granted: March 26, 2024
Patent Number: 11941437
Systems, apparatuses and methods provide technology for batch-level parallelism, including partitioning a graph into a plurality of clusters comprising batched clusters that support batched data and non-batched clusters that fail to support batched data, establishing an execution queue for execution of the plurality of clusters based on cluster dependencies, and scheduling inference execution of the plurality of clusters in the execution queue based on batch size. The technology can…

Methods, systems, and apparatuses for a multiprocessor boot flow for a faster boot process

Granted: March 26, 2024
Patent Number: 11941409
Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code…

Methods and apparatus for intentional programming for heterogeneous systems

Granted: March 26, 2024
Patent Number: 11941400
Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first…

Apparatuses, methods, and systems for instructions for 16-bit floating-point matrix dot product instructions

Granted: March 26, 2024
Patent Number: 11941395
Systems, methods, and apparatuses relating to 16-bit floating-point matrix dot product instructions are described. In one embodiment, a processor includes fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a M by N destination matrix having single-precision elements, an M by K first source matrix, and a K by N second source matrix, the source matrices having elements that each comprise a pair of half-precision floating-point values, the…

Data element rearrangement, processors, methods, systems, and instructions

Granted: March 26, 2024
Patent Number: 11941394
A processor includes a decode unit to decode an instruction indicating a source packed data operand having source data elements and indicating a destination storage location. Each of the source data elements has a source data element value and a source data element position. An execution unit, in response to the instruction, stores a result packed data operand having result data elements each having a result data element value and a result data element position. Each result data element…

Microcode(uCode) hot-upgrade method for bare metal cloud deployment

Granted: March 26, 2024
Patent Number: 11941391
A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system…

Mechanism to provide visual feedback regarding computing system command gestures

Granted: March 26, 2024
Patent Number: 11941181
A mechanism to provide visual feedback regarding computing system command gestures. An embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the…

Device and method for route planning

Granted: March 26, 2024
Patent Number: 11940287
Provided is a device and a method for route planning. The route planning device (100) may include a data interface (128) coupled to a road and traffic data source (160); a user interface (170) configured to display a map and receive a route planning request from a user, the route planning request including a line of interest on the map; a processor (110) coupled to the data interface (128) and the user interface (170). The processor (110) may be configured to identify the line of…

Fuse recipe update mechanism

Granted: March 26, 2024
Patent Number: 11940944
A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.

Technologies for memory tagging

Granted: March 26, 2024
Patent Number: 11940927
Techniques for memory tagging are disclosed. In the illustrative embodiment, 16 bits of a virtual memory address are used as memory tag bits. In a page table entry corresponding to the virtual memory address, page tag bits indicate which of the 16 bits of the virtual memory address are to be sent to the memory as memory tag bits when a memory operation is requested on the virtual memory address. The memory can then compare the memory tag bits sent with the physical memory address to…

Methods and apparatus for sparse tensor storage for neural network accelerators

Granted: March 26, 2024
Patent Number: 11940907
Methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. An example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage…

Apparatus and method for dynamic reallocation of processor power by throttling processor to allow an external device to operate

Granted: March 26, 2024
Patent Number: 11940855
Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power…

Hinge mechanism for foldable devices with flexible displays

Granted: March 26, 2024
Patent Number: 11940851
In one embodiment, a hinge apparatus includes two curved rack apparatuses, each curved rack apparatus defining an arcuate surface and an arcuate set of gear teeth concentric with the arcuate surface, where the radius of curvature of the arcuate set of gear teeth being non-uniform. The hinge apparatus further includes a gear assembly that includes a first gear, a second gear, a third gear coupling the first and second gears, a fourth gear coupling the first gear and the arcuate set of…

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Granted: March 26, 2024
Patent Number: 11940824
Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described…

Navigating semi-autonomous mobile robots

Granted: March 26, 2024
Patent Number: 11940797
Techniques for navigating semi-autonomous mobile robots are described. A semi-autonomous mobile robot moves within an environment to complete a task. A navigation server communicates with the robot and provides the robot information. The robot includes a navigation map of the environment, interaction information, and a security level. To complete the task, the robot transmits a route reservation request to the navigation server, the route reservation request including a priority for the…

Stressed silicon modulator

Granted: March 26, 2024
Patent Number: 11940678
An optical modulator includes a substrate, a first dielectric layer over the substrate, a rib waveguide including a PN junction on the first dielectric, a second dielectric layer over the rib waveguide and a stressor layer including a metal, where the first or the second dielectric is between the stressor layer and the PN junction.

Illuminator with phase scrambling particles

Granted: March 26, 2024
Patent Number: 11940633
An illuminator has phase scrambling particles to reduce speckle.