Systems, methods, and apparatuses for tile matrix multiplication and accumulation
Granted: November 19, 2024
Patent Number:
12147804
Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to…
Metal oxide liner for cross-point phase change memory cell
Granted: November 19, 2024
Patent Number:
12150391
Phase change memory material stacks having a metal oxide liner for memory integrated circuits, related systems, and methods of fabrication are disclosed. Such phase change memory material stacks include a phase change material and a switching device and the sidewalls of the phase change memory material stacks are lined with a metal oxide to protect the material stacks during manufacture and use and to provide isolation between the material stacks.
Electrical interconnect bridge
Granted: November 19, 2024
Patent Number:
12148704
Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS…
EMIB patch on glass laminate substrate
Granted: November 19, 2024
Patent Number:
12148703
Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.
Compute optimizations for low precision machine learning operations
Granted: November 19, 2024
Patent Number:
12148063
One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point…
Malicious request detection in automated resource dispatch
Granted: November 19, 2024
Patent Number:
12148061
Systems and techniques for malicious request detection in automated resource dispatch are described herein. A request for a resource may be received from a user device. A location may be obtained for delivery of the resource. Sensor data may be retrieved for the location. The sensor data and user profile data may be evaluated to determine if the request is malicious. A disincentivizing message may be generated based on the determination that the request is malicious. In response to…
Compression for deep learning in case of sparse values mapped to non-zero value
Granted: November 19, 2024
Patent Number:
12147914
Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the…
Work stealing in heterogeneous computing systems
Granted: November 19, 2024
Patent Number:
12147849
Methods, apparatus, systems, and articles of manufacture are disclosed to steal work in heterogeneous computing systems. An apparatus includes load balancing circuitry to obtain tasks from a workload by encoding minimum and maximum index ranges of a data parallel operation, allocate a first task from the workload to a first work queue based on a first capability of first computation circuitry, the first computation circuitry to process the first task in the first work queue, and allocate…
Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning accelerators
Granted: November 19, 2024
Patent Number:
12147836
Techniques and configurations enhancing the performance of hardware (HW) accelerators are provided. A schedule-aware, dynamically reconfigurable, tree-based partial sum accumulator architecture for HW accelerators is provided, where the depth of an adder tree in the HW accelerator is dynamically based on a dataflow schedule generated by a compiler. The adder tree depth is adjusted on a per-layer basis at runtime. Configuration registers, programmed via software, dynamically alter the…
Methods and apparatus to insert profiling instructions into a graphics processing unit kernel
Granted: November 19, 2024
Patent Number:
12147809
Embodiments are disclosed for inserting profiling instructions into graphics processing unit (GPU) kernels. An example apparatus includes instructions, and at least one processor to execute the instructions to determine whether a GPU supports modification of entry point addresses, detect a first entry point address and a second entry point address of an original GPU kernel, create a corresponding instrumented GPU kernel from the original GPU kernel based on the determination by inserting…
Flexible vapor chamber with shape memory material
Granted: November 19, 2024
Patent Number:
12146476
Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.
High performance memory module with reduced loading
Granted: November 19, 2024
Patent Number:
12147698
An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a…
Techniques for image-based search using touch controls
Granted: November 19, 2024
Patent Number:
12147662
Techniques for image-based search using touch controls are described. An apparatus may comprise: a processor circuit; a gesture component operative on the processor circuit to receive gesture information from a touch-sensitive screen displaying an image and generate a selection area corresponding to the gesture information; a capture component operative on the processor circuit to extract an image portion of the image corresponding to the selection area; and a search component operative…
Performance monitoring unit of a processor deterring tampering of counter configuration and enabling verifiable data sampling
Granted: November 19, 2024
Patent Number:
12147532
A secure performance monitoring unit of a processor includes one or more performance monitoring counters and a secure group manager. The secure group manager is configured to receive a request to create a secure counter group from a software (SW) process being executed by a processor, the request including identification of the one or more counters; determine availability of the one or more counters, creating the secure counter group, assign the one or more counters to the secure counter…
Method and apparatus for shared virtual memory to manage data coherency in a heterogeneous processing system
Granted: November 19, 2024
Patent Number:
12147346
Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory…
Systems and methods for error detection and control for embedded memory and compute elements
Granted: November 19, 2024
Patent Number:
12147302
Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local…
Power and thermal management in a solid state drive
Granted: November 19, 2024
Patent Number:
12147286
Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.
First-in first-out buffer with lookahead performance booster
Granted: November 19, 2024
Patent Number:
12147262
A FIFO may use lookahead circuitry to boost performance and reduce data transfer latency by reducing the FIFO operation cycles when operating in the store and forward mode. The lookahead circuitry may increase data transfer rate of the FIFO between two integrated circuit devices that use different clock frequencies. The use of the lookahead circuitry with the FIFO may also reduce power consumption of the FIFO, allow storage media of the FIFO to be smaller, and free up valuable die space…
Hybrid manufacturing for integrating photonic and electronic components
Granted: November 19, 2024
Patent Number:
12147083
Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides,…
Dynamically adjusting an infrastructure item
Granted: November 19, 2024
Patent Number:
12146643
Disclosure herein are systems and methods for dynamically adjusting infrastructure items, such as street lights, construction signage, and/or other lighting elements. The systems and methods may include receiving environmental data for a sector containing the infrastructure items. A quality of infrastructure effectors located within the sector may be determined. A deviation from a standard infrastructure quality associated with the infrastructure effectors may be determined. A setting of…
