Graphics system with additional context
Granted: April 29, 2025
Patent Number:
12288287
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a…
Multi-tenant isolated data regions for collaborative platform architectures
Granted: April 29, 2025
Patent Number:
12289362
A multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. Instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, MKTME), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and…
Transistor with isolation below source and drain
Granted: April 29, 2025
Patent Number:
12288803
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation…
Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact
Granted: April 29, 2025
Patent Number:
12288789
Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source…
Microelectronic assemblies
Granted: April 29, 2025
Patent Number:
12288751
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
Conformal power delivery structure for direct chip attach architectures
Granted: April 29, 2025
Patent Number:
12288750
In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between…
Skip level vias in metallization layers for integrated circuit devices
Granted: April 29, 2025
Patent Number:
12288746
An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in…
Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
Granted: April 29, 2025
Patent Number:
12288744
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
Semiconductor package with hybrid mold layers
Granted: April 29, 2025
Patent Number:
12288740
According to various examples, a device is described. The device may include a first package substrate. The device may also include a first mold layer with a first thickness. The device may also include a second mold layer with a second thickness proximal to the first mold layer. The second thickness may be larger than the first thickness. The first mold layer may include a plurality of first interconnects coupled to the first package substrate. The second mold layer may include a…
Balancing alternate frame times on a variable refresh rate display
Granted: April 29, 2025
Patent Number:
12288534
In one embodiment, a new frame is to be presented on a display. A frame time is predicted for the new frame along with a current balance for a set of previously presented frames. A frame pattern for the new frame is determined based on the predicted frame time and the current balance.
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
Granted: April 29, 2025
Patent Number:
12287843
Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the…
Dynamic routing of texture loads in graphics processing
Granted: April 29, 2025
Patent Number:
12288284
Dynamic routing of texture-load in graphics processing is described. An example of a processor includes one or more processing resources, the one or more processing resources to load a message including a texture load; a texture sampler and a data port; and a message router to route the texture load to a destination, wherein the destination may be either the texture sampler or the data port; wherein the message router includes arbitration circuitry to select the destination for the…
Out-of-order pixel shading and rasterization
Granted: April 29, 2025
Patent Number:
12288283
Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution…
Adaptively embedding visual advertising content into media content
Granted: April 29, 2025
Patent Number:
12288224
Technologies for adaptively embedding visual advertising content into media content include a computing device for receiving visual advertisements, an advertisement map, and media content from a remote content provider. Such technologies may also include determining a location of an advertising enabled area within an image of the media content, selecting a visual advertisement to embed within the image of the media content at the determined location of the advertising enabled area as a…
Assessment and response mechanism for autonomous systems
Granted: April 29, 2025
Patent Number:
12288166
Various systems and methods for implementing an assessment and response mechanism for autonomous systems are described herein. An assessment and response system for an autonomous system is configured to access a realm classification of an event; determine a hazard score based on the realm classification, a severity metric, a likelihood metric, an urgency metric, and a confidence level metric; identify, based on the hazard score, a responsive action; and record details of the hazard score…
Schedule-aware tensor distribution module
Granted: April 29, 2025
Patent Number:
12288153
Methods and systems include a neural network system that includes a neural network accelerator. The neural network accelerator includes multiple processing engines coupled together to perform arithmetic operations in support of an inference performed using the deep neural network system. The neural network accelerator also includes a schedule-aware tensor data distribution circuitry or software that is configured to load tensor data into the multiple processing engines in a load phase,…
Multi-level caching for dynamic deep learning models
Granted: April 29, 2025
Patent Number:
12288141
Systems, apparatuses and methods provide technology for model generation with intermediate stage caching and re-use, including generating, via a model pipeline, a multi-level set of intermediate stages for a model, caching each of the set of intermediate stages, and responsive to a change in the model pipeline, regenerating an executable for the model using a first one of the cached intermediate stages to bypass regeneration of at least one of the intermediate stages. The multi-level set…
Technologies for dividing work across accelerator devices
Granted: April 29, 2025
Patent Number:
12288101
Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of…
Methods, systems, apparatus, and articles of manufacture to extend the life of embedded processors
Granted: April 29, 2025
Patent Number:
12288095
Methods, systems, apparatus, and articles of manufacture to extend the life of embedded processors are disclosed herein. Disclosed example apparatus include a policy selector to select a policy, based on input information. The apparatus extends an operating lifespan of a microprocessor having a plurality of cores. The apparatus also includes a cores partitioner to divide, based on the selected policy, the plurality of cores into subsets of cores, including a first subset and a second…
Providing a partial reconfiguration (PR) bitstream to a cloud service provider for PR configuration of an accelerator device
Granted: April 29, 2025
Patent Number:
12287909
An apparatus to facilitate enabling secure communication via attestation of multi-tenant configuration on accelerator devices is disclosed. The apparatus includes a processor to: verify a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP); generate a partial reconfiguration (PR) bitstream based on the base bitstream, the PR bitstream to fit within at least one PR region of PR boundary setups of the accelerator device; inspect…
