Intel Patent Grants

Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

Granted: July 16, 2024
Patent Number: 12039001
Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

Distributed radiohead system

Granted: July 16, 2024
Patent Number: 12041540
Various aspects provide a radiohead circuit and a communication device including the radiohead circuit. In an example, the radiohead circuit includes an antenna interface, a radio frequency front end configured to receive a wireless communication signal via the antenna interface, and a processor configured to perform an initial signal detection to detect if a wireless communication signal has been received based on whether a signal the processor received from the radio frequency front…

Machine learning accelerator mechanism

Granted: July 16, 2024
Patent Number: 12039435
An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Deep learning numeric data and sparse matrix compression

Granted: July 16, 2024
Patent Number: 12039421
An apparatus to facilitate deep learning numeric data and sparse matrix compression is disclosed. The apparatus includes a processor comprising a compression engine to: receive a data packet comprising a plurality of cycles of data samples, and for each cycle of the data samples: pass the data samples of the cycle to a compressor dictionary; identify, from the compressor dictionary, tags for each of the data samples, wherein the compressor dictionary comprises at least a first tag for…

Packed data element predication processors, methods, systems, and instructions

Granted: July 16, 2024
Patent Number: 12039336
A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has…

Systems, methods, and apparatus for matrix move

Granted: July 16, 2024
Patent Number: 12039332
Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

Instructions and logic to perform floating point and integer operations for machine learning

Granted: July 16, 2024
Patent Number: 12039331
One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein…

Methods, systems, and apparatuses to optimize partial flag updating instructions via dynamic two-pass execution in a processor

Granted: July 16, 2024
Patent Number: 12039329
Systems, methods, and apparatuses relating to circuitry to implement dynamic two-pass execution of a partial flag updating instruction in a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into a set of one or more micro-operations, an execution circuit to execute the micro-operations decoded for the instructions, a data register to store data, a flag register to store a plurality of flags, and a reservation station…

Apparatus and method for quantum computing performance simulation

Granted: July 16, 2024
Patent Number: 12039234
Apparatus and method for a full quantum system simulator. For example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of…

Cryptographic enforcement of borrow checking across groups of pointers

Granted: July 16, 2024
Patent Number: 12039033
Techniques for borrow checking in hardware are described. The technology includes a memory to store a plurality of allocated objects, an allocated object referenced by a pointer; and a processor to execute a join instruction to create a group of pointers, by creating a group record for the group referenced by a group pointer and setting a group bit and ownership identifier (ID) of pointers of the group; and execute a transfer group ownership instruction to transfer ownership of the…

Handheld device, dock and corresponding methods and systems

Granted: July 16, 2024
Patent Number: 12036467
Examples relate to a handheld device, a dock for a handheld device, and to corresponding methods and systems. The handheld device comprises a main unit comprising a display of the handheld device. The handheld device comprises two input controllers being non-removably attached to the main unit via an extension mechanism. The extension mechanism is configured such, that the two input controllers are movable from a retracted configuration to an extended configuration.

Matrix operation optimization mechanism

Granted: July 16, 2024
Patent Number: 12039000
An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve…

System decoder for training accelerators

Granted: July 16, 2024
Patent Number: 12038861
There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator…

Processor package with universal optical input/output

Granted: July 16, 2024
Patent Number: 12038858
A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical…

Technologies for dynamic input/output data transfer rate scaling based on power policy engine

Granted: July 16, 2024
Patent Number: 12038854
Techniques for controlling input/output (I/O) power usage are disclosed. In the illustrative embodiment, a power policy engine of a compute device monitors power usage, I/O data transfer rates, and temperature and determines when there should be a change in an I/O power setting. The I/O data transfer requires that the data be handled properly, causing the compute device to expend power on the I/O data transfer. The power policy engine may instruct a device driver, such as a driver of an…

Hardware software communication channel to support direct programming interface methods on FPGA-based prototype platforms

Granted: July 16, 2024
Patent Number: 12038819
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the…

Bipolar time-to-digital converter

Granted: July 16, 2024
Patent Number: 12038725
A bipolar TDC apparatus with a phase detection and signal switching circuitry and a phase error measurement circuitry. The phase detection and signal switching circuitry include a multiplexer and phase detector, together referred to as PD_MUX. The PD_MUX is used to handle the order of the two input signal phases of a TDC, or in other words, to enable TDC the bipolarity detection of the phase error. The apparatus detects first the polarity of the phase error and then prepares the right…

Precisely controlled chirped diode laser and coherent LIDAR system

Granted: July 16, 2024
Patent Number: 12038511
A light detection and ranging (LIDAR) system may include a laser source configured to emit one or more optical beams; a scanning optical system configured to scan the one or more optical beams over a scene and capture reflections of the one or more optical beams from the scene; a measurement system configured to divide the scene into a plurality of pixels, the measurement system comprising a detector configured to detect a return signal from multiple pixels of the plurality of pixels as…

Chemical compositions and methods of patterning microelectronic device structures

Granted: July 16, 2024
Patent Number: 12037434
A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of…

Interconnect structure surface modifications by passivating agents

Granted: July 16, 2024
Patent Number: 12036578
Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization…