Intel Patent Grants

Automated secure data and firmware migration between removable storage devices that supports boot partitions and replay protected memory blocks

Granted: January 15, 2019
Patent Number: 10180800
Systems, apparatuses and methods may include technology that detects a migration request and conducts a first transfer, via a trusted execution environment (TEE), of storage context information from a first removable storage device to a secure memory region of a system in response to the data migration request. Additionally, the technology may conduct a second transfer, via the TEE, of the storage context information from the secure memory region to a second removable storage device,…

Multi-register gather instruction

Granted: January 15, 2019
Patent Number: 10180838
A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand that identifies content that indicates multiple vector registers, a first set of indexes of each of the vector registers that each identifies a source data element, and a second set of indexes of the destination vector register for each identified source element. The instruction is decoded and executed, causing, for each of the…

Processor extensions to identify and avoid tracking conflicts between virtual machine monitor and guest virtual machine

Granted: January 15, 2019
Patent Number: 10180854
A processing system includes an execution unit, communicatively coupled to an architecturally-protected memory, the execution unit comprising a logic circuit to execute a virtual machine monitor (VMM) that supports a virtual machine (VM) comprising a guest operating system (OS) and to implement an architecturally-protected execution environment, wherein the logic circuit is to responsive to executing a blocking instruction by the guest OS directed at a first page stored in the…

Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping

Granted: January 15, 2019
Patent Number: 10180856
A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and dispatching a plurality of instructions from a plurality of select ports in a scheduler module in first clock cycle. Next, it comprises determining if a first physical register file unit has capacity to support instructions dispatched in the first clock cycle. Further, it comprises supplying a response back to logic circuitry…

Hybrid hardware and software implementation of transactional memory access

Granted: January 15, 2019
Patent Number: 10180903
Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations…

Synchronizing a translation lookaside buffer with an extended paging table

Granted: January 15, 2019
Patent Number: 10180911
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Device, system and method for communication with heterogeneous physical layers

Granted: January 15, 2019
Patent Number: 10180927
A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange…

Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions

Granted: January 15, 2019
Patent Number: 10180928
Heterogeneous hardware accelerator architectures for processing sparse matrix data having skewed non-zero distributions are described. An accelerator includes sparse tiles to access data from a first memory over a high bandwidth interface and very/hyper sparse tiles to randomly access data from a second memory over a low-latency interface. The accelerator determines that one or more computational tasks involving a matrix are to be performed, partitions the matrix into a first plurality…

Methods and apparatus for automatically implementing a compensating reset for retimed circuitry

Granted: January 15, 2019
Patent Number: 10181001
A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under reset. The device configuration circuitry may provide an adjustment sequence length as well as a start signal to the initialization module to properly reset the retimed user logic implemented on the integrated circuit after initial configuration and unfreezing of the integrated circuit. The auto initialization module may control the…

Multi-package integrated circuit assembly with package on package interconnects

Granted: January 15, 2019
Patent Number: 10181456
A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A conductive interconnect can be electrically coupled from the interface…

Selective epitaxially grown III-V materials based devices

Granted: January 15, 2019
Patent Number: 10181518
A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Ungrounded shield for an electrical connector

Granted: January 15, 2019
Patent Number: 10181682
Particular embodiments described herein provide for a connector shield that can include a main body, a shield portion to shield electromagnetic radiation from a connector, and a support portion. The main body can be removably secured to the connector. The shield portion includes lossy material and the shield portion is not grounded. The connector can include connection lines and the connection lines are at least partially inside a cavity of the shield portion.

Digital phase locked loop frequency estimation

Granted: January 15, 2019
Patent Number: 10181856
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

Apparatus, system and method of beamforming training

Granted: January 15, 2019
Patent Number: 10181886
Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of…

Apparatuses and methods for reducing switching jitter

Granted: January 15, 2019
Patent Number: 10181940
Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.

Flexible architecture and instruction for advanced encryption standard (AES)

Granted: January 15, 2019
Patent Number: 10181945
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

Cryptographic protection of I/O data for DMA capable I/O controllers

Granted: January 15, 2019
Patent Number: 10181946
Technologies for cryptographic protection of I/O data include a computing device with one or more I/O controllers. Each I/O controller may generate a direct memory access (DMA) transaction that includes a channel identifier that is indicative of the I/O controller and that is indicative of an I/O device coupled to the I/O controller. The computing device intercepts the DMA transaction and determines whether to protect the DMA transaction as a function of the channel identifier. If so,…

Downstream device service latency reporting for power management

Granted: January 15, 2019
Patent Number: 10182398
An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface controller to communicate with an endpoint device. The interface controller is coupled to the processor and configured to access a register of the endpoint device, the register to be mapped into a memory space of the system, the register to store a service latency tolerance value of the endpoint device. The endpoint device has a service…

Apparatus, system and method of indicating a time offset using a grant frame

Granted: January 15, 2019
Patent Number: 10182437
Some demonstrative embodiments include apparatuses, devices, systems and methods of dynamic allocation using a grant frame. For example, a wireless station may be able to generate a grant frame including a duration field and a Dynamic Allocation Info field, the Dynamic Allocation Info field including an allocation duration subfield and an access mode subfield, the access mode subfield to indicate an access mode of an allocation according to the grant frame; and to transmit the grant…

Apparatus, system and method of selecting a wireless communication channel

Granted: January 15, 2019
Patent Number: 10182446
Some demonstrative embodiments include apparatuses, systems and/or methods of selecting a wireless communication channel to communicate in a wireless communication network. For example, an apparatus may include a channel selector to select at a network controller of a first wireless communication network a first wireless communication channel to communicate between the network controller and one or more wireless communication devices, to detect on the first wireless communication channel…