Intel Patent Grants

Channel reservation for operation in an unlicensed spectrum

Granted: October 17, 2017
Patent Number: 9794821
Embodiments described herein relate generally to a communication between a user equipment (“UE”) and an evolved Node Bs (“eNBs”) in a plurality of frequency bands. An eNB may transmit cross-carrier, cross-subframe scheduling information to a UE in a licensed frequency band. In response reception of the scheduling information, the UE may sense a wireless transmission medium to determine if the medium is idle. If the medium is idle, the UE may generate and transmit a request to…

Flexible adjustment of uplink and downlink ratio configuration

Granted: October 17, 2017
Patent Number: 9794859
An apparatus and method for flexible adjustment of the uplink-downlink ratio configuration for each enhanced node B (eNodeB) within a wireless communications network is disclosed herein. In one embodiment, a given eNodeB is configured to determine a current or subsequent uplink-downlink ratio configuration for a pre-determined time period. The determined current or subsequent uplink-downlink ratio configuration is encoded into a special physical downlink control channel (PDCCH), the…

User equipment and method for user equipment feedback of flow-to-rat mapping preferences

Granted: October 17, 2017
Patent Number: 9794870
An embodiment of methods and user equipment are disclosed. Once such method includes a user equipment transmitting preferences for Flow-to-RAT mapping to a base station of a network. The user equipment may receive a Flow-to-RAT mapping from the base station that specifies a particular RAT to be associated with a particular Flow.

Extended paging discontinuous reception (DRX) cycles in wireless communication networks

Granted: October 17, 2017
Patent Number: 9794876
Embodiments of wireless communication devices and method for discontinuous reception (DRX) mode in RRC_IDLE state of wireless communication are generally described herein. Some of these embodiments describe a wireless communication device having processing circuitry arranged to determine to use an extended paging discontinuous reception (DRX) value to increase a paging cycle length. The wireless communication device may transmit a non-access stratum (NAS) message to the network,…

Ocean-deployed subsurface sensor location positioning system

Granted: October 17, 2017
Patent Number: 9791538
The disclosure generally relates to a method, apparatus and system to deploy aquatic sensors to obtain oceanographic data. In an exemplary embodiment, a free-floating or untethered sensor receives signals from different transmitters. The signals may be configured to travel through air and/or water. The sensor records each signals' time of arrival and determines its location in relationship to known transmitters based on the signal travel time. The position of each sensor may be…

Inverted 45° mirror for photonic integrated circuits

Granted: October 17, 2017
Patent Number: 9791641
Inverted 45° semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45° semiconductor mirror functions to couple light between a plane in the PIC chip defined by thin film layers and a direction normal to a top surface of the PIC chip where it may be generated or collected by an off-chip component, such as a wire terminal. In an exemplary embodiment, a (110) plane of a cubic crystalline semiconductor may provide a…

Fast digital to time converter linearity calibration to improve clock jitter performance

Granted: October 17, 2017
Patent Number: 9791834
A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold.…

Method to realize reconfigurable memory topology

Granted: October 17, 2017
Patent Number: 9791899
An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T…

Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure

Granted: October 17, 2017
Patent Number: 9792222
Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address…

Reducing latency by persisting data relationships in relation to corresponding data in persistent memory

Granted: October 17, 2017
Patent Number: 9792224
A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

Protecting a memory

Granted: October 17, 2017
Patent Number: 9792229
In an embodiment, a processor includes: at least one core to execute instructions; and a memory protection logic to encrypt data to be stored to a memory coupled to the processor, generate a message authentication code (MAC) based on the encrypted data, the MAC to have a first value according to a first key, obtain the encrypted data from the memory and validate the encrypted data using the MAC, where the MAC is to be re-keyed to have a second value according to a second key and without…

Secure direct memory access

Granted: October 17, 2017
Patent Number: 9792234
Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also include allowing decrypted content obtained as encrypted content from a source memory to be placed at a destination memory based on whether destination memory addresses for the destination memory fall within the secure destination address range.

Ramping inhibit voltage during memory programming

Granted: October 17, 2017
Patent Number: 9792997
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up…

Energy storage device, method of manufacturing same, and mobile electronic device containing same

Granted: October 17, 2017
Patent Number: 9793061
An energy storage device comprises a first porous semiconducting structure (510) comprising a first plurality of channels (511) that contain a first electrolyte (514) and a second porous semiconducting structure (520) comprising a second plurality of channels (521) that contain a second electrolyte (524). In one embodiment, the energy storage device further comprises a film (535) on at least one of the first and second porous semiconducting structures, the film comprising a material…

Stiffener tape for electronic assembly

Granted: October 17, 2017
Patent Number: 9793151
Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting…

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Granted: October 17, 2017
Patent Number: 9793159
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating…

Systems, methods and devices for opportunistic networking

Granted: October 17, 2017
Patent Number: 9794033
Opportunistic networking systems can utilize one or multiple bands/channels that are shared with other radio access technologies (RATs) (such as wireless local area networks (WLAN, such as Wi-Fi) and mmWave). An unconventional carrier type (UCT) can be defined to support opportunistic networking in licensed and/or unlicensed spectrum. For example, a primary base station can determine a secondary base station activated for use with user equipment (UE). The primary base station can…

Distribution of forwarded clock

Granted: October 17, 2017
Patent Number: 9794055
A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A…

Wireline receiver circuitry having collaborative timing recovery

Granted: October 17, 2017
Patent Number: 9794089
Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal.…

Methods and devices for interference variance estimation and interference cancellation

Granted: October 17, 2017
Patent Number: 9794097
An interference variance estimation method includes receiving a composite sample comprising a sample of a first OFDM transmission scheme interfered by out-of-band interference of a second OFDM transmission scheme; determining for each of the resource elements of the first transmission scheme a power estimate of the out-of-band interference; and filtering the power estimates over subcarriers corresponding to a same symbol, wherein weights of the filtering are based on a correlation…