Systems, methods and devices for determining work placement on processor cores
Granted: May 6, 2025
Patent Number:
12293237
Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by…
Semiconductor device having doped epitaxial region and its methods of fabrication
Granted: May 6, 2025
Patent Number:
12294027
Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.
Gate-all-around integrated circuit structures having insulator substrate
Granted: May 6, 2025
Patent Number:
12294006
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is…
Integrated circuit structures including backside vias
Granted: May 6, 2025
Patent Number:
12294003
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer…
Boiling enhancement structures for immersion cooled electronic systems
Granted: May 6, 2025
Patent Number:
12293956
An apparatus is described. The apparatus includes a packaged semiconductor device. The packaged semiconductor device having an integrated heat spreader, wherein, a boiling enhancement structure exists on the integrated heat spreader without a block mass residing between the boiling enhancement structure and the integrated heat spreader. The boiling enhancement structure has a structured non-planar surface to promote bubble nucleation in an immersion cooling system.
Directed self-assembly enabled subtractive metal patterning
Granted: May 6, 2025
Patent Number:
12293913
Described herein are IC devices include tight-pitched patterned metal layers, such as metal gratings, and processes for forming such patterned metal layers. The processes include subtractive metal patterning, where portions of a metal layer are etched and replaced with an insulator to form the metal grating. Masks for etching portions of the metal layer are generated using directed self-assembly (DSA). In some examples, multiple etching steps are performed, e.g., to generate metal lines…
Road hazard communication
Granted: May 6, 2025
Patent Number:
12293661
Apparatus, systems, and/or methods may involve reporting a road hazard. Road hazard data may be collected for an object on a road, which may include automatically generated data from a device associated with the object causing a hazard. The road hazard data may be provided to a service, an application, a device, a client, and so on. For example, the road hazard data may be merged with a map and provided to a map services client, a navigation client, and so on. An alert may be generated…
Tile sequencing mechanism
Granted: May 6, 2025
Patent Number:
12293462
An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
Sparse optimizations for a matrix accelerator architecture
Granted: May 6, 2025
Patent Number:
12293431
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.
Typed unordered access view overloading on pixel pipeline
Granted: May 6, 2025
Patent Number:
12293430
Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource,…
Gallium nitride (GaN) integrated circuit technology with optical communication
Granted: May 6, 2025
Patent Number:
12292608
Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the…
Packet processing load balancer
Granted: May 6, 2025
Patent Number:
12293231
Examples described herein include a device interface; a first set of one or more processing units; and a second set of one or more processing units. In some examples, the first set of one or more processing units are to perform heavy flow detection for packets of a flow and the second set of one or more processing units are to perform processing of packets of a heavy flow. In some examples, the first set of one or more processing units and second set of one or more processing units are…
Systems and methods to store a tile register pair to memory
Granted: May 6, 2025
Patent Number:
12293186
Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right…
Firmware component with self-descriptive dependency information
Granted: May 6, 2025
Patent Number:
12293182
An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.
Method and apparatus to perform a multiple bit column read using a single bit per column memory accessible by row and/or by column
Granted: May 6, 2025
Patent Number:
12293107
A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the…
Method, system and apparatus to prevent denial of service attacks on PCIe based computing devices
Granted: May 6, 2025
Patent Number:
12292975
The disclosure generally relates method, system and apparatus to prevent denial of service (DOS) attacks on PCIe based computing devices. In an exemplary embodiment, an independent register is used in combination with a filter driver and additional logic to form an integrity check for power down instructions. An exemplary system includes a register circuitry corresponding to the IP device, the register circuitry having a designated storage bit to indicate an unlocked state of the…
Methods and apparatus to transmit and/or receive data streams with a network interface controller
Granted: May 6, 2025
Patent Number:
12292844
Methods, apparatus, systems, and articles of manufacture to transmit and/or receive data streams with a network interface controller are disclosed. An example apparatus includes a direct memory access engine to fetch a descriptor for a data transmission from system memory; and determine a time to generate an interrupt based on the descriptor; a scheduler to trigger the interrupt when the time occurs, the interrupt to cause an application to sample data and store the sampled data as a…
Network layer 7 offload to infrastructure processing unit for service mesh
Granted: May 6, 2025
Patent Number:
12292842
Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and…
Secure direct peer-to-peer memory access requests between devices
Granted: May 6, 2025
Patent Number:
12292840
An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.
Systems and methods for isolating an accelerated function unit and/or an accelerated function context
Granted: May 6, 2025
Patent Number:
12292791
Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining…
