Apparatuses, methods, and systems toprecisely monitor memory store accesses
Granted: April 8, 2025
Patent Number:
12271735
Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the…
Methods and apparatus to calibrate and/or validate stereoscopic depth sensing systems
Granted: April 8, 2025
Patent Number:
12273500
Methods and apparatus to calibrate and/or validate stereoscopic depth sensing systems are disclosed. An example apparatus includes an image generator to generate a first image for a first image sensor; and generate a second image for a second image sensor. First content in the first image is to be shifted relative to corresponding second content in the second image by a shift amount. The shift amount based on a target depth to be tested. The example apparatus further includes a…
Privacy-preserving augmented and virtual reality using homomorphic encryption
Granted: April 8, 2025
Patent Number:
12273327
An improved AR/VR operation includes receiving, by a server computing device, encrypted AR/VR user data and cleartext metadata associated with the encrypted AR/VR user data from a client computing device; getting server data based at least in part on cleartext metadata; encoding the server data; performing an AR/VR process on the encrypted AR/VR user data and the encoded server data to generate encrypted AR/VR results; and sending the encrypted AR/VR results to the client computing…
Congestion management techniques
Granted: April 8, 2025
Patent Number:
12273270
Examples described herein relate to a network element comprising an ingress pipeline and at least one queue from which to egress packets. The network element can receive a packet and generate a congestion notification packet at the ingress pipeline to a sender of the packet based on detection of congestion in a target queue that is to store the packet and before the packet is stored in a congested target queue. The network element can generate a congestion notification packet based on a…
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
Granted: April 8, 2025
Patent Number:
12272727
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer.…
Heterogeneous nested interposer package for IC chips
Granted: April 8, 2025
Patent Number:
12272656
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise…
Microelectronic package with substrate cavity for bridge-attach
Granted: April 8, 2025
Patent Number:
12272650
Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.
Integrated circuit packages with solder thermal interface materials with embedded particles
Granted: April 8, 2025
Patent Number:
12272614
Disclosed herein are integrated circuit (IC) packages with solder thermal interface materials (STIMs) with embedded particles, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, a die between the package substrate and the lid and a STIM between the die and the lid. The STIM may include embedded particles, and at least some of the embedded particles may have a diameter equal to a distance between the die and the…
Topology shader technology
Granted: April 8, 2025
Patent Number:
12271991
Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
Cluster identifier remapping for asymmetric topologies
Granted: April 8, 2025
Patent Number:
12271760
A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of…
Multi-port memory link expander to share data among hosts
Granted: April 8, 2025
Patent Number:
12271329
Systems, apparatuses and methods may provide for technology that collects, by a BIOS (basic input output system), memory information from a first host path to a coherent device memory on a memory expander, wherein the memory expander includes a plurality of host paths, transfers the memory information from the BIOS to an OS (operating system) via one or more OS interface tables, and initializes, by the OS, the memory expander based on the memory information, wherein the memory…
Device, system, and method for inspecting direct memory access requests
Granted: April 8, 2025
Patent Number:
12271327
Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based…
Controller for locking of selected cache regions
Granted: April 8, 2025
Patent Number:
12271308
Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is…
Integrated three-dimensional (3D) DRAM cache
Granted: April 8, 2025
Patent Number:
12271306
Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to…
Power-based adaptive hardware reliability on a device
Granted: April 8, 2025
Patent Number:
12271248
System and techniques for power-based adaptive hardware reliability on a device are described herein. A hardware platform is divided into multiple partitions. Here, each partition includes a hardware component with an adjustable reliability feature. The several partitions are placed into one of multiple reliability categories. A workload with a reliability requirement is obtained and executed on a partition in a reliability category that satisfies the reliability requirements. A change…
Restricted area autonomous vehicle control techniques
Granted: April 8, 2025
Patent Number:
12271198
Various systems and methods for providing autonomous driving within a restricted area are discussed. In an examples, an autonomous vehicle control system can include an interface for receiving data from multiple sensors for detecting an environment about the vehicle, a security processor coupled to the configured to receive sensor information from the sensor interface, and autonomous driving system including one or more virtual machines configured to selectively receive information from…
Scene intelligence for collaborative semantic mapping with mobile robots
Granted: April 8, 2025
Patent Number:
12270657
Various aspects of techniques, systems, and use cases include provide instructions for operating an autonomous mobile robot (AMR). A technique may include capturing audio or video data using a sensor of the AMR, performing a classification of the audio or video data using a trained classifier, and identifying a coordinate of an environmental map corresponding to a location of the audio or video data. The technique may include updating the environmental map to include the classification…
Methods and apparatus to dynamically control devices based on distributed data
Granted: April 1, 2025
Patent Number:
12267389
Methods, apparatus, systems and articles of manufacture to dynamically control devices based on distributed data are disclosed. An example apparatus includes a comparator to compare a first measurement measured by a first peer device to a second measurement, the second measurement being measured locally by the apparatus; and an operation adjuster to, when the comparison satisfies a threshold, adjust a measurement protocol of the first peer device.
Hybrid pitch through hole connector
Granted: April 1, 2025
Patent Number:
12267957
Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch…
Seamless access to trusted domain protected memory by virtual machine manager using transformer key identifier
Granted: April 1, 2025
Patent Number:
12267423
In one embodiment, an apparatus includes a processor comprising at least one core to execute instructions of a plurality of virtual machines (VMs) and a virtual machine monitor (VMM), and a cryptographic engine to protect data associated with the plurality of VMs through use of a plurality of private keys and a trusted transformer key, where each of the plurality of private keys are to protect program instructions and data of a respective VM and the trusted transformer key is to protect…
