Detection of video tampering
Granted: May 6, 2025
Patent Number:
12294731
Techniques are provided for generation of secure video and tamper detection of the secure video. A methodology implementing the techniques according to an embodiment includes selecting a subset of macroblocks from a video frame to be transmitted and calculating a low frequency metric on each of the selected macroblocks. The method also includes performing a hash calculation on the low frequency metrics to generate a frame signature, encrypting the frame signature (using a private key) to…
Road hazard communication
Granted: May 6, 2025
Patent Number:
12293661
Apparatus, systems, and/or methods may involve reporting a road hazard. Road hazard data may be collected for an object on a road, which may include automatically generated data from a device associated with the object causing a hazard. The road hazard data may be provided to a service, an application, a device, a client, and so on. For example, the road hazard data may be merged with a map and provided to a map services client, a navigation client, and so on. An alert may be generated…
Sparse optimizations for a matrix accelerator architecture
Granted: May 6, 2025
Patent Number:
12293431
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.
Typed unordered access view overloading on pixel pipeline
Granted: May 6, 2025
Patent Number:
12293430
Methods, systems and apparatuses provide for graphics processor technology that routes untyped unordered access view (UAV) messages to a next level memory cache, routes typed UAV messages and render target messages to a pixel pipeline, and processes, via the pixel pipeline, the typed UAV messages. The technology can also provide for the pixel pipeline to perform a format conversion of one or more pixels associated with a typed UAV message based on a surface format of a UAV resource,…
Network layer 7 offload to infrastructure processing unit for service mesh
Granted: May 6, 2025
Patent Number:
12292842
Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and…
Gallium nitride (GaN) integrated circuit technology with optical communication
Granted: May 6, 2025
Patent Number:
12292608
Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the…
Semiconductor device having tipless epitaxial source/drain regions
Granted: April 29, 2025
Patent Number:
12288821
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in…
Multi-tenant isolated data regions for collaborative platform architectures
Granted: April 29, 2025
Patent Number:
12289362
A multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. Instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, MKTME), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and…
Dynamic load balancing for multi-core computing environments
Granted: April 29, 2025
Patent Number:
12289239
Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores…
Clock manager monitoring for time synchronized networks
Granted: April 29, 2025
Patent Number:
12289161
Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a…
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
Granted: April 29, 2025
Patent Number:
12287843
Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the…
Gate-all-around integrated circuit structures having insulator fin on insulator substrate
Granted: April 29, 2025
Patent Number:
12288813
Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of…
Backside contact structures and fabrication for metal on both sides of devices
Granted: April 29, 2025
Patent Number:
12288810
An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to…
High aspect ratio source or drain structures with abrupt dopant profile
Granted: April 29, 2025
Patent Number:
12288808
Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement…
Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly
Granted: April 29, 2025
Patent Number:
12288807
A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.
Transistor with isolation below source and drain
Granted: April 29, 2025
Patent Number:
12288803
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation…
Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact
Granted: April 29, 2025
Patent Number:
12288789
Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source…
Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
Granted: April 29, 2025
Patent Number:
12288744
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
Instructions for fused multiply-add operations with variable precision input operands
Granted: April 29, 2025
Patent Number:
12288062
Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit…
Providing a partial reconfiguration (PR) bitstream to a cloud service provider for PR configuration of an accelerator device
Granted: April 29, 2025
Patent Number:
12287909
An apparatus to facilitate enabling secure communication via attestation of multi-tenant configuration on accelerator devices is disclosed. The apparatus includes a processor to: verify a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP); generate a partial reconfiguration (PR) bitstream based on the base bitstream, the PR bitstream to fit within at least one PR region of PR boundary setups of the accelerator device; inspect…
