System management mode runtime resiliency manager
Granted: April 8, 2025
Patent Number:
12271325
A system management mode (SMM) runtime resiliency manager (SRM) augments computing resource protection policies provided by an SMM policy shim. The SMM shim protects system resources by deprivileging system management interrupt (SMI) handlers to a lower level of privilege (e.g., ring 3 privilege) and by configuring page tables and register bitmaps (e.g., I/O, MSR, and Save State register bitmaps). SRM capabilities include protecting the SMM shim, updating the SMM shim, protecting a…
Multi-link operation for a single radio multi-link device
Granted: April 8, 2025
Patent Number:
12273964
This disclosure describes systems, methods, and devices related to multi-link operation. A device may configure a single N×N transmit (TX)/receive (RX) radio to a plurality of 1×1 TX/RX radios, where N is a positive integer. The device may monitor a first channel of a plurality of channels to determine its availability. The device may monitor a second channel of the plurality of channels to determine its availability. The device may identify a first control frame received from an…
Coreless electronic substrates having embedded inductors
Granted: April 8, 2025
Patent Number:
12272484
An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching…
Duty cycle adjuster optimization training algorithm to minimize the jitter associated with DDR5 DRAM transmitter
Granted: April 8, 2025
Patent Number:
12272426
Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA…
Topology shader technology
Granted: April 8, 2025
Patent Number:
12271991
Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.
Cluster identifier remapping for asymmetric topologies
Granted: April 8, 2025
Patent Number:
12271760
A first plurality of integrated circuit blocks of a first chip are connected to a second plurality of integrated circuit blocks of a second chip. A cluster remapping table is provided on the second chip and is to be programmed to identify a desired asymmetric topology of the connections between the first plurality of integrated circuit blocks and the second plurality of integrated circuit blocks. Logic is to discover the actual topology of the connections between the first plurality of…
Apparatuses, methods, and systems toprecisely monitor memory store accesses
Granted: April 8, 2025
Patent Number:
12271735
Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the…
Independently controlled DMA and CPU access to a shared memory region
Granted: April 8, 2025
Patent Number:
12271616
An embodiment of an integrated circuit comprises circuitry to share page tables associated with a page between a processor memory management unit (MMU) and an input/output memory management unit (IOMMU), store a page table entry in the memory associated with the page, and separately control access to the page from a processor and from a direct memory access (DMA) request based on one or more fields of the stored page table entry. Other embodiments are disclosed and claimed.
Multi-port memory link expander to share data among hosts
Granted: April 8, 2025
Patent Number:
12271329
Systems, apparatuses and methods may provide for technology that collects, by a BIOS (basic input output system), memory information from a first host path to a coherent device memory on a memory expander, wherein the memory expander includes a plurality of host paths, transfers the memory information from the BIOS to an OS (operating system) via one or more OS interface tables, and initializes, by the OS, the memory expander based on the memory information, wherein the memory…
Device, system, and method for inspecting direct memory access requests
Granted: April 8, 2025
Patent Number:
12271327
Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based…
Scene intelligence for collaborative semantic mapping with mobile robots
Granted: April 8, 2025
Patent Number:
12270657
Various aspects of techniques, systems, and use cases include provide instructions for operating an autonomous mobile robot (AMR). A technique may include capturing audio or video data using a sensor of the AMR, performing a classification of the audio or video data using a trained classifier, and identifying a coordinate of an environmental map corresponding to a location of the audio or video data. The technique may include updating the environmental map to include the classification…
Data stored or free space based FIFO buffer
Granted: April 8, 2025
Patent Number:
12271319
Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are…
Controller for locking of selected cache regions
Granted: April 8, 2025
Patent Number:
12271308
Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is…
Integrated three-dimensional (3D) DRAM cache
Granted: April 8, 2025
Patent Number:
12271306
Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to…
Two-level main memory hierarchy management
Granted: April 8, 2025
Patent Number:
12271305
A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and…
Power-based adaptive hardware reliability on a device
Granted: April 8, 2025
Patent Number:
12271248
System and techniques for power-based adaptive hardware reliability on a device are described herein. A hardware platform is divided into multiple partitions. Here, each partition includes a hardware component with an adjustable reliability feature. The several partitions are placed into one of multiple reliability categories. A workload with a reliability requirement is obtained and executed on a partition in a reliability category that satisfies the reliability requirements. A change…
Restricted area autonomous vehicle control techniques
Granted: April 8, 2025
Patent Number:
12271198
Various systems and methods for providing autonomous driving within a restricted area are discussed. In an examples, an autonomous vehicle control system can include an interface for receiving data from multiple sensors for detecting an environment about the vehicle, a security processor coupled to the configured to receive sensor information from the sensor interface, and autonomous driving system including one or more virtual machines configured to selectively receive information from…
Light detection and ranging systems and optical system
Granted: April 8, 2025
Patent Number:
12270941
A light detection and ranging system is provided using a first electromagnetic radiation of a first emitting structure as local oscillator signal for a second electromagnetic radiation received from the outside of the light detection and ranging system, wherein the first and second electromagnetic radiations are coherent and the resulting signal is detected by a detecting structure. The resulting signal corresponds to an information of a target at the outside of the light detection and…
Methods and apparatus to trigger calibration of a sensor node using machine learning
Granted: April 8, 2025
Patent Number:
12270886
Methods, apparatus, systems and articles of manufacture to trigger calibration of a sensor node using machine learning are disclosed. An example apparatus includes a machine learning model trainer to train a machine learning model using first sensor data collected from a sensor node. A disturbance forecaster is to, using the machine learning model and second sensor data, forecast a temporal disturbance to a communication of the sensor node. A communications processor is to transmit a…
Apparatus and method for protecting probe card and probes using thermal heat sensor trace
Granted: April 8, 2025
Patent Number:
12270831
An apparatus includes a thermal heat sensor trace including conductive metal and disposed in a space transformer, the thermal heat sensor trace being configured to form a resistance, and a controller configured to sense a voltage across the resistance formed by the thermal heat sensor trace, the voltage positively correlating to a temperature of the space transformer. The controller is further configured to determine whether the sensed voltage is greater than or equal to a predetermined…
