Technologies for data migration between edge accelerators hosted on different edge locations
Granted: April 30, 2024
Patent Number:
11972298
Technologies for migrating data between edge accelerators hosted on different edge locations include a device hosted on a present edge location. The device includes one or more processors to: receive a workload from a requesting device, determine one or more accelerator devices hosted on the present edge location to perform the workload, and transmit the workload to the one or more accelerator devices to process the workload. The one or more processor is further to determine whether to…
Wake up receiver frame
Granted: April 30, 2024
Patent Number:
11974227
This disclosure describes systems, methods, and devices related to wake up receiver (WUR) frequency division multiple access (FDMA) transmission. A device may cause to send a wake up receiver (WUR) beacon frame on a WUR beacon operating channel to one or more station devices. The device may determine a first wake-up frame to be sent on a first WUR operating channel, wherein the first WUR operating channel is associated with one or more frequency division multiple access (FDMA) channels…
Chiplet first architecture for die tiling applications
Granted: April 30, 2024
Patent Number:
11973041
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further…
Internal node jumper for memory bit cells
Granted: April 30, 2024
Patent Number:
11973032
Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate…
1D vertical edge blocking (VEB) via and plug
Granted: April 30, 2024
Patent Number:
11972979
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined…
Cinematic space-time view synthesis for enhanced viewing experiences in computing environments
Granted: April 30, 2024
Patent Number:
11972780
A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. The method further includes…
Integrated image sensor and display pixel
Granted: April 30, 2024
Patent Number:
11972635
In one example, a display includes an array of display pixels. Each display pixel includes at least one light-emitting diode. At least one of the display pixels includes an image sensor.
Apparatus and method of guided neural network model for image processing
Granted: April 30, 2024
Patent Number:
11972545
The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize…
Learning neural reflectance shaders from images
Granted: April 30, 2024
Patent Number:
11972519
Described herein are techniques for learning neural reflectance shaders from images. A set of one or more machine learning models can be trained to optimize an illumination latent code and a set of reflectance latent codes for an object within a set of input images. A shader can then be generated based on a machine learning model of the one or more machine learning models. The shader is configured to sample the illumination latent code and the set of reflectance latent codes for the…
Methods, apparatus, and systems to dynamically schedule workloads among compute resources based on temperature
Granted: April 30, 2024
Patent Number:
11972303
Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also…
Busbar
Granted: April 30, 2024
Patent Number:
D1024974
Quality of service rules in allocating processor resources
Granted: April 30, 2024
Patent Number:
11972291
An apparatus and method for conditional quality of service in a processor. For example, one embodiment of a processor comprises: a plurality of processor resources to be allocated to a plurality of executed processes in accordance with a set of quality of service (QoS) rules; and conditional quality of service (QoS) circuitry/logic to monitor usage of the plurality of processor resources by the plurality of processes and to responsively modify an allocation of a first processor resource…
Device enhancements for software defined silicon implementations
Granted: April 30, 2024
Patent Number:
11972269
Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the…
Matrix transpose and multiply
Granted: April 30, 2024
Patent Number:
11972230
Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution…
Configuring display screen coordinates
Granted: April 30, 2024
Patent Number:
11972165
Methods, apparatus, systems, and articles of manufacture are disclosed for configuring display screen coordinates. An example apparatus includes at least one storage device or storage disk, instructions, and at least one processor to execute the instructions. When executed, the example instructions cause the at least one processor to determine whether a first position of a first display screen is within a threshold of a second position of a second display screen, and in response to…
Data relocation for inline metadata
Granted: April 30, 2024
Patent Number:
11972126
Technologies disclosed herein provide one example of a system that includes processor circuitry to be communicatively coupled to a memory circuitry. The processor circuitry is to receive a memory access request corresponding to an application for access to an address range in a memory allocation of the memory circuitry and to locate a metadata region within the memory allocation. The processor circuitry is also to, in response to a determination that the address range includes at least a…
Technologies for securely providing remote accelerators hosted on the edge to client compute devices
Granted: April 30, 2024
Patent Number:
11972001
Technologies for securely providing one or more remote accelerators hosted on edge resources to a client compute device includes a device that further includes an accelerator and one or more processors. The one or more processors are to determine whether to enable acceleration of an encrypted workload, receive, via an edge network, encrypted data from a client compute device, and transfer the encrypted data to the accelerator without exposing content of the encrypted data to the one or…
Link layer-PHY interface adapter
Granted: April 30, 2024
Patent Number:
11971841
An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband…
Methods, systems, articles of manufacture and apparatus to control address space isolation in a virtual machine
Granted: April 30, 2024
Patent Number:
11971827
Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value,…
Bendable and foldable display screen to provide continuous display
Granted: April 30, 2024
Patent Number:
11971754
Embodiments are generally directed to a flexible overlapping display. An embodiment of a mobile device includes a processor to process data for the mobile device, a bendable and foldable display screen, one or more device sensors to sense an orientation of the mobile device, and one or more display sensors to sense a current arrangement of the display screen. The processor is to identify one or more portions of the display screen that are visible to a user based at least in part on data…
