Memory cells having increased structural stability
Granted: February 25, 2025
Patent Number:
12239032
A memory cell can include a top lamina layer, a bottom lamina layer, and a phase change material (PCM) layer between the top lamina layer and the bottom lamina layer. The PCM layer can have a top surface in direct contact with the top lamina layer and a bottom surface in direct contact with the bottom lamina layer. The top surface of the PCM layer and the bottom surface of the PCM layer can have a structurally stabilizing width ratio.
Two transistor memory cell using stacked thin-film transistors
Granted: February 25, 2025
Patent Number:
12238913
Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the…
Immersion cooling for integrated circuit devices
Granted: February 25, 2025
Patent Number:
12238892
A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment,…
Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication
Granted: February 25, 2025
Patent Number:
12237223
Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the…
Sparsity-aware datastore for inference processing in deep neural network architectures
Granted: February 18, 2025
Patent Number:
12229673
Systems, apparatuses and methods may provide for technology that prefetches compressed data and a sparsity bitmap from a memory to store the compressed data in a decode buffer, where the compressed data is associated with a plurality of tensors, wherein the compressed data is in a compressed format. The technology aligns the compressed data with the sparsity bitmap to generate decoded data, and provides the decoded data to a plurality of processing elements.
Redundant sub-pixels in a light-emitting diode display
Granted: February 18, 2025
Patent Number:
12230181
A display device includes light-emitting diode (LED) devices to implement an array of pixels, where pixels in the array are each associated with a respective first set of LED devices to implement a first set of sub-pixels and a respective second set of LED devices to implement a redundant second set of sub-pixels for the corresponding pixel. Controller circuitry is provided to alternatively enable the first set of LED devices or the second set of LED device to implement the sub-pixels of…
Object-based volumetric video coding
Granted: February 18, 2025
Patent Number:
12230002
Methods, apparatus, systems and articles of manufacture for object-based volumetric video coding are disclosed. An example apparatus disclosed herein includes a point annotator to receive point cloud data associated with an object and annotate points of the point cloud data with an object identifier of the object. The disclosed example apparatus also includes a projector to project the point cloud data onto projection planes to produce texture images and geometry images. The disclosed…
Motion biased foveated renderer
Granted: February 18, 2025
Patent Number:
12229871
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled…
Apparatus and method for acceleration data structure refit
Granted: February 18, 2025
Patent Number:
12229870
Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the…
Graphics architecture including a neural network pipeline
Granted: February 18, 2025
Patent Number:
12229867
One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural…
Occupancy verification device and method
Granted: February 18, 2025
Patent Number:
12228939
An occupancy verification including one or more processors, configured to receive occupancy grid data representing a plurality of cells of an occupancy grid and for each cell of the plurality of cells, a probability of whether the cell is occupied; receive object location data, representing one or more locations of one or more objects identified using a model; map the object location data to one or more cells of the plurality of cells based on the one or more locations of the one or more…
Disaggregated computing for distributed confidential computing environment
Granted: February 18, 2025
Patent Number:
12229605
An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest…
Virtualization and multi-tenancy support in graphics processors
Granted: February 18, 2025
Patent Number:
12229581
Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics…
Methods and apparatus for deep learning network execution pipeline on multi-processor platform
Granted: February 18, 2025
Patent Number:
12229569
Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.
Multi-variate strided read operations for accessing matrix operands
Granted: February 18, 2025
Patent Number:
12229560
In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix…
Instruction and logic for tracking fetch performance bottlenecks
Granted: February 18, 2025
Patent Number:
12229558
A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the…
BFLOAT16 fused multiply instructions
Granted: February 18, 2025
Patent Number:
12229554
Techniques for performing BF16 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate…
Memory management device for performing DMA operations between a main memory and a cache memory
Granted: February 18, 2025
Patent Number:
12229051
Memory modules and associated devices and methods are provided using a memory copy function between a cache memory and a main memory that may be implemented in hardware. Address translation may additionally be provided.
Device, system and method for identifying a source of latency in pipeline circuitry
Granted: February 18, 2025
Patent Number:
12229034
Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at…
System power management in multi-port I/O hybrid systems
Granted: February 18, 2025
Patent Number:
12228992
In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or…
