System for address mapping and translation protection
Granted: March 18, 2025
Patent Number:
12253958
This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs)…
Systems and methods for module configurability
Granted: March 18, 2025
Patent Number:
12256467
A component (e.g. a module configuration system) of a device may include an interface and processor circuitry. The processor circuitry may be configured to: determine identification information of a hardware device (e.g. module, microchip) connected to the component via the interface; obtain device information for the connected hardware device based on the determined identification information; and initialize the connected hardware device based on the obtained device information.
Quick user datagram protocol (UDP) internet connections (QUIC) packet offloading
Granted: March 18, 2025
Patent Number:
12255974
Embodiments include a method of opening a Quick User Datagram Protocol (UDP) Internet Connections (QUIC) socket on a computing platform, initializing QUIC packet processing of a hardware-based offloader, opening a QUIC connection to the offloader, and transmitting a first QUIC packet to the offloader over the QUIC connection. The hardware-based offloader encrypts and transmits the QUIC packet.
Efficient encryption in VPN sessions
Granted: March 18, 2025
Patent Number:
12255921
Methods, apparatus, and software for efficient encryption in virtual private network (VPN) sessions. A VPN link and an auxiliary link (and associated sessions) are established between computing platforms to support end-to-end communication between respective application running on the platforms. The VPN link may employ a conventional VPN protocol such as TLS or IPsec, while the auxiliary link comprises a NULL encryption VPN tunnel. To transfer data, a determination is made to whether the…
Differentiated containerization and execution of web content based on trust level and other attributes
Granted: March 18, 2025
Patent Number:
12255897
Systems and methods may provide for receiving web content and determining a trust level associated with the web content. Additionally, the web content may be mapped to an execution environment based at least in part on the trust level. In one example, the web content is stored to a trust level specific data container.
Application-level network queueing
Granted: March 18, 2025
Patent Number:
12255830
There is disclosed in one example a network interface card (NIC), comprising: an ingress interface to receive incoming traffic; a plurality of queues to queue incoming traffic; an egress interface to direct incoming traffic to a plurality of server applications; and a queuing engine, including logic to: uniquely associate a queue with a selected server application; receive an incoming network packet; determine that the selected server application may process the incoming network packet;…
Scalable toggle point control circuitry for a clustered decode pipeline
Granted: March 18, 2025
Patent Number:
12254319
Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster,…
Message authentication Galois integrity and correction (MAGIC) for lightweight row hammer mitigation
Granted: March 18, 2025
Patent Number:
12254203
The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.
Apparatuses and methods to accelerate matrix multiplication
Granted: March 18, 2025
Patent Number:
12254061
Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector…
PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states
Granted: March 18, 2025
Patent Number:
12253966
A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power…
Magneto-optical Kerr effect interconnects for photonic packaging
Granted: March 18, 2025
Patent Number:
12253722
An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and…
Methods, systems, articles of manufacture and apparatus to control address space isolation in a virtual machine
Granted: March 18, 2025
Patent Number:
12253955
Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value,…
Software-defined coherent caching of pooled memory
Granted: March 18, 2025
Patent Number:
12253948
Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete…
Disk caching and/or tiering with device internal busy information
Granted: March 18, 2025
Patent Number:
12253945
Systems, apparatuses and methods may provide for technology that detects, via a processor external to a solid state drive (SSD), internal information associated with the SSD, detects background operations with respect to the SSD based on the internal information, wherein the background operations include one or more of current operations or predicted operations, and adjusts a hierarchical data placement policy based on the background operations.
Systems, apparatuses, and methods for autonomous functional testing of a processor
Granted: March 18, 2025
Patent Number:
12253925
Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power…
Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices
Granted: March 18, 2025
Patent Number:
12253901
Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured…
Gating of a mesh clock signal in a processor
Granted: March 18, 2025
Patent Number:
12253877
In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated…
Real-time anomaly detection for industrial processes
Granted: March 18, 2025
Patent Number:
12253849
In one embodiment, a device comprises interface circuitry and processing circuitry. The processing circuitry receives, via the interface circuitry, a video stream captured by a camera during performance of an industrial process, wherein the video stream comprises a sequence of frames; detects, based on analyzing the sequence of frames, a degree of particle scatter that occurs during performance of the industrial process; and determines, based on the degree of particle scatter, that an…
Fiber shuffle embedded optical connector
Granted: March 18, 2025
Patent Number:
12253724
Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, a compute die over the package substrate, and an optics die over the package substrate. In an embodiment, the optics die comprises grating couplers. In an embodiment, an optical connector for optically coupling optical fibers to the grating couplers is provided. In an embodiment, the optical connector comprises a fiber array unit (FAU), where the FAU has a turn. In…
Shallow-profile optical elements for photonics receivers
Granted: March 18, 2025
Patent Number:
12253723
An optical system can include a optical receiver comprising an optical waveguide, an optical lid adjacent the waveguide, and a reflective surface proximate an output of the optical waveguide to direct light from the waveguide towards an output of the optical lid. The optical system can also include a photodetector (PD) die comprising a substrate, a concave mirror, and a photodetector. The concave mirror is formed on a first side of the substrate and the photodetector is disposed on a…
