OPTICAL SENSORS FOR DETECTING RELATIVE MOTION AND/OR POSITION AND METHODS AND SYSTEMS FOR USING SUCH OPTICAL SENSORS
Granted: December 13, 2012
Application Number:
20120312962
A system according to an embodiment of the present invention includes one or more first optical sensors and one or more second optical sensors. The first optical sensor(s) each include a photodetector region and a plurality of first slats over the photodetector region. The second optical sensor(s) each include a photodetector region and a plurality of second slats over the photodetector region, wherein the second slats have a different configuration than the first slats. For example, the…
SYSTEMS AND METHODS FOR FACILITATING LIFT-OFF PROCESSES
Granted: November 22, 2012
Application Number:
20120293474
Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the…
SYSTEMS AND METHODS FOR FORMING ISOLATED DEVICES IN A HANDLE WAFER
Granted: November 15, 2012
Application Number:
20120288083
A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the…
CLEAR LAYER ISOLATION
Granted: November 15, 2012
Application Number:
20120290255
A method for optical isolation in a clear mold package is provided. The method comprises forming a substrate and mounting a first component on the substrate. The method also comprises depositing a clear layer over the first component and the substrate and fabricating a trench in the clear layer near the first component, wherein the trench extends from a top surface of the substrate to the top surface of the clear layer. Further, the method comprises depositing an opaque material within…
ADAPTIVE CHARGE PUMP
Granted: November 1, 2012
Application Number:
20120274392
A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold…
GRADIENT-BASED APPROACH TO SAMPLE-TIME MISMATCH ERROR CALIBRATION IN A TWO-CHANNEL TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
Granted: November 1, 2012
Application Number:
20120274491
Correcting phase error in a two-channel TIADC system in a manner that is independent of the Nyquist zone(s) occupied by the input signal. In the preferred approach this is done using the gradient of a phase error estimate. The gradient may be determined from a simplified expression of linear regression; the direction of the adaptation is then controlled by the sign of the gradient. The adaptive algorithm converges to the optimal value regardless of the Nyquist zone occupied by the input…
CHARGING SYSTEM WITH ADAPTIVE POWER MANAGEMENT
Granted: October 25, 2012
Application Number:
20120268063
An embodiment of a charger may include an input, at least one switch having a first node coupled to a reference voltage, a current sensor coupled between the input and a second node of the at least one switch, an output coupled to a third node of the at least one switch, and a charge controller coupled to the input to determine an input voltage, to the current sensor to determine an input current and to control inputs of the at least one switch. The at least one switch may be responsive…
NEGATIVE CAPACITANCE SYNTHESIS FOR USE WITH DIFFERENTIAL CIRCUITS
Granted: October 25, 2012
Application Number:
20120268206
Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the…
ROBUST GAIN AND PHASE CALIBRATION METHOD FOR A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
Granted: October 25, 2012
Application Number:
20120268299
A time-interleaved analog to digital converter (TIADC) that uses a digital filter to remove sampling-frequency symmetries that might otherwise degrade error correction. In an embodiment, two Analog to Digital Converter (ADC) cores provide a set of two ADC outputs. Interleaving the digital signals output by the ADC cores forms a digital representation of the input signal. The ADC cores have an offset correction input, a gain correction input, or a sample time correction input. Prior to…
VOTER TESTER FOR REDUNDANT SYSTEMS
Granted: October 25, 2012
Application Number:
20120272109
A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response…
METHOD AND STRUCTURE FOR REDUCING GATE LEAKAGE CURRENT AND POSITIVE BIAS TEMPERATURE INSTABILITY DRIFT
Granted: October 18, 2012
Application Number:
20120261767
Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer…
FAULT TOLERANT REDUNDANT CLOCK CIRCUIT
Granted: October 18, 2012
Application Number:
20120262208
A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal.…
SYSTEM AND METHOD FOR ACTIVE ELECTROMAGNETIC INTERFERENCE REDUCTION FOR A SWITCHING CONVERTER
Granted: October 18, 2012
Application Number:
20120262139
An EMI reduction network for a converter, the converter including upper and lower power switches provided between an input voltage node and a reference node. An inductance is coupled between the input voltage node and the upper switch at a first node, a capacitance and an auxiliary power switch are coupled in series between the first and reference nodes, and a controller is provided to control switching. The controller switches the upper switch based on a PWM signal. The controller keeps…
ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES
Granted: October 18, 2012
Application Number:
20120261836
A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation…
MONOLITHIC INTEGRATED CAPACITORS FOR HIGH-EFFICIENCY POWER CONVERTERS
Granted: October 11, 2012
Application Number:
20120256193
A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output…
SYSTEM AND METHOD FOR PROGRAMMING AND CONTROLLING OVER CURRENT TRIP POINT LIMITS IN VOLTAGE REGULATORS
Granted: October 11, 2012
Application Number:
20120257312
A system and method for controlling an over current protection trip point for a voltage regulator includes an input for receiving a monitored operating parameter of the voltage regulator. Control logic responsive to this input generates a digital current control signal. A digital to analog controller converts the digital current control signal to an analog current control signal and this analog current control signal is used for controlling a current source for generating a current that…
HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS
Granted: October 4, 2012
Application Number:
20120248627
A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example…
SWITCH MULTIPLEXER DEVICES WITH EMBEDDED DIGITAL SEQUENCERS
Granted: October 4, 2012
Application Number:
20120254803
A switch multiplexer device comprises a plurality of analog switches, and an embedded digital sequencer in operative communication with the analog switches. The embedded digital sequencer including a plurality of sequence control registers. The embedded digital sequencer is configured to transmit control information to the analog switches, with the control information including single or extended control information. The extended control information is employed to pre-load operational…
DEVICES INCLUDING BOND PAD HAVING PROTECTIVE SIDEWALL SEAL
Granted: September 27, 2012
Application Number:
20120241893
A device having a detector includes a sensor package. The sensor package includes a light sensor, at least one filter located over the light sensor and at least one bond pad. The light sensor is formed on a semiconductor device that provides sensor information related to light incident upon the light sensor. A perimeter of each bond pad is covered by a protective layer forming a sidewall seal. The sensor package also includes a package that encases the light sensor, filter(s) and bond…
CHARGING SYSTEM WITH ADAPTIVE POWER MANAGEMENT
Granted: September 20, 2012
Application Number:
20120235630
An embodiment of a charger may include an input, at least one switch having a first node coupled to a reference voltage, a current sensor coupled between the input and a second node of the at least one switch, an output coupled to a third node of the at least one switch, and a charge controller coupled to the input to determine an input voltage, to the current sensor to determine an input current and to control inputs of the at least one switch. The at least one switch may be responsive…
