Power device with a plastic molded package and direct bonded substrate
Granted: April 27, 2004
Patent Number:
6727585
A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second…
Reverse blocking IGBT
Granted: April 27, 2004
Patent Number:
6727527
A power device includes a semiconductor substrate of first conductivity type. The semiconductor substrate includes a front-side surface, a backside surface, and a scribe region. The substrate has a first well of second conductivity type whereon an active cell is defined. The first well has a first impurity type of a first mobility. A continuous diffusion region of second conductivity type extends from the front-side surface to the backside surface. The continuous diffusion region…
Non-uniform power semiconductor device
Granted: March 23, 2004
Patent Number:
6710405
An active area of a power device comprises active cells having designs that vary depending on where they are located in the active area. Design variations include structural variations and variations in the material used to produce the cells.
Electrically isolated power semiconductor package
Granted: March 23, 2004
Patent Number:
6710463
A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die…
Rugged and fast power MOSFET and IGBT
Granted: January 27, 2004
Patent Number:
6683344
A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.
Method for manufacturing a power semiconductor device and direct bonded substrate thereof
Granted: December 30, 2003
Patent Number:
6670216
Embodiments of the present invention are directed to packaged power semiconductor devices and direct-bonded metal substrates thereof. In one embodiment, a method for manufacturing a power semiconductor device comprises inserting a substrate assembly into a furnace having a plurality of process zones. The substrate assembly includes a first aluminum layer and a second aluminum layer that are electrically isolated from each other by a dielectric layer. The method further comprises…
CMOS compatible band gap reference
Granted: December 2, 2003
Patent Number:
6657480
A CMOS low noise band gap reference circuit outputs a substantially constant reference voltage VREF. The band gap reference circuit has an amplifier that includes a differential pair of bipolar junction transistors and a feedback circuit that adjusts its current to compensate for variations in the bias current through the circuit. The band gap reference circuit provides an output reference voltage VREF that is substantially constant over a range of temperature and a range of supply…
Stable high voltage semiconductor device structure
Granted: November 4, 2003
Patent Number:
6642551
A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings…
Method of manufacturing gate driver with level shift circuit
Granted: October 28, 2003
Patent Number:
6638808
A method for forming a gate driver configured to drive a power semiconductor device includes providing a substrate having an upper surface; forming a conductive region on a portion of the upper surface of the substrate; forming a dielectric layer overlying the conductive region; forming a first conductive layer provided over the conductive region and at least a portion of the dielectric layer; patterning the first conductive layer to provide the first conductive layer with a given…
Differential amplifier having active load device scaling
Granted: June 24, 2003
Patent Number:
6583665
In a CMOS differential amplifier, first and second input transistors are matched in size to each other, and first and second load transistors are matched in size to each other. The first input transistor, a source follower transistor, and the first load transistor form one current branch of the differential structure while the second input transistor and second load transistor form another current branch of the differential structure. A first current source supplies current to both…
Electrically isolated power device package
Granted: June 24, 2003
Patent Number:
6583505
A packaged power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The substrate has a lower surface. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package…
Method of making electrically isolated power semiconductor package
Granted: March 18, 2003
Patent Number:
6534343
A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die…
Power semiconductor module
Granted: January 14, 2003
Patent Number:
6507108
The invention relates to a power semiconductor module (10) having a baseplate (1) on which at least one substrate (13) is arranged which is fitted with power semiconductor chips (11, 12) and can be pressed via pressure elements and contact cords (17) against the baseplate (1). The baseplate (1) has centering elements on which a frame (3) which defines fields (7) and is in the form of a grid is provided, with corresponding substrates (13) with power semiconductor chips being arranged in…
Low noise and low offset bipolar input amplifiers
Granted: January 14, 2003
Patent Number:
6507239
The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor. The differential pair has a single ended output coupled to the input of a…
Semiconductor device with trenched substrate and method
Granted: November 27, 2001
Patent Number:
6323090
A transistor structure has a recess formed in the upper surface of its base layer, an epitaxial (epi) layer grown on the upper surface in a manner to create a surface depression in the outer surface of the epi layer, the surface depression being generally aligned with the recess. A semiconductor element, such as a well or a gate, is formed on the epi layer aligned with the recess.
Stable high voltage semiconductor device structure
Granted: October 23, 2001
Patent Number:
6306728
A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings…
High voltage transistors and thyristors
Granted: December 19, 2000
Patent Number:
6162665
A high voltage transistor or thyristor having a base layer which is a thinned neutron transmuted wafer 102, 152 instead of a diffused or epitaxially grown base layer. The neutron transmuted wafer has high resistivity and a desired thickness while the layer formed overlying the surface of the neutron transmuted wafer has a desired thickness and doping level. Adjusting the thicknesses and doping levels within these two structures produce a device having the desire high voltage…
Isolated multi-chip devices
Granted: November 14, 2000
Patent Number:
6147393
A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer…
Isolated multi-chip devices
Granted: August 22, 2000
Patent Number:
6107674
A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer…
Reverse blocking IGBT
Granted: July 18, 2000
Patent Number:
6091086
A method of forming a power integrated circuit device (100) including a semiconductor layer of first conductivity type. The semiconductor layer includes a front-side surface (103), a backside surface (116), and a scribe region (117). The semiconductor layer further including a plurality of active cells on the front-side surface (103). The present method includes forming a backside layer (116) of second conductivity type overlying the backside surface, and forming a continuous diffusion…
