Semiconductor power package with three leads
Granted: February 22, 2000
Patent Number:
D420983
Method of making a stable high voltage semiconductor device structure
Granted: May 18, 1999
Patent Number:
5904544
A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings…
High voltage power MOS device
Granted: December 22, 1998
Patent Number:
5851857
A switching device is described having a semiconductor substrate with a front side and a back side. The switching device includes a first transistor which includes a first region adjacent the front side, a second region within the first region, the semiconductor substrate, and at least one island region adjacent the backside. The switching device also includes a second transistor which includes the first region, the second region, the semiconductor substrate, and a third region coupled…
High frequency MOS device
Granted: September 1, 1998
Patent Number:
5801419
A high frequency power MOS device (90) that is built by MOS technology having high speed switching capability. The device provides improved turn-on and turn-off capabilities by providing gate interconnects comprising substantially metallization, thereby reducing parasitic resistance and capacitance. The device may be fabricated by a MOS process relying upon a dual metallization layer (127, 133) for forming the interconnects. The dual metallization layer has substantially less resistivity…
Voltage transient suppression circuit for preventing overvoltages in power transistor systems
Granted: March 24, 1998
Patent Number:
5731729
An apparatus for suppressing voltage transients across a first transistor is described. The first transistor has a first terminal, a second terminal, and a gate terminal, and is characterized by an avalanche breakdown voltage rating between the first and second terminals. The cathode of a first diode is coupled to the first terminal, the first diode having a reverse breakdown voltage which is less than the avalanche breakdown voltage rating. Gate driver circuitry is provided by which the…
Method of making a reverse blocking IGBT
Granted: December 16, 1997
Patent Number:
5698454
A method of forming a power integrated circuit device (100) including a semiconductor layer of first conductivity type. The semiconductor layer includes a front-side surface (103), a backside surface (116), and a scribe region (117). The semiconductor layer further including a plurality of active cells on the front-side surface (103). The present method includes forming a backside layer (116) of second conductivity type overlying the backside surface, and forming a continuous diffusion…
Power semiconductor module having a plastic housing a metal/ceramic multilayer substrate and terminals in a soft encapsulation
Granted: December 16, 1997
Patent Number:
5699232
A power semiconductor module includes a plastic housing having a bottom plane in which a substrate is disposed. Disposed inside the module are the substrate, structures on the substrate, a rubber-like soft encapsulation and a hard encapsulation above the soft encapsulation. Internal struts of the housing extend into the soft encapsulation and, if appropriate, have ends with transverse extensions disposed within the soft encapsulation. The effect of this module construction is that a back…
Stable high voltage semiconductor device structure
Granted: May 13, 1997
Patent Number:
5629552
A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings…
Intelligent, isolated half-bridge power module
Granted: January 21, 1997
Patent Number:
5596466
A power module having at least one power transistor. Each power transistor is coupled to and protected by an overvoltage clamp and desaturation detection circuit. An output current measurement system is coupled to the power module output. A junction temperature sensor is coupled to each power transistor. An isolation transformer is associated with each power transistor, the primary windings of which are connected to an isolated driver communications interface which converts logic signals…
Advanced power device process for low drop
Granted: August 6, 1996
Patent Number:
5543335
A method for fabricating a power semiconductor device with a low forward voltage drop using polymer passivation. A polymer passivation layer is deposited over the device. Impurities are introduced into the backside of the device by ion implantation, the backside of the device being on the opposite side of the semiconductor device from the polymer passivation layer. The impurities are then diffused into the semiconductor device.
Overvoltage clamp and desaturation detection circuit
Granted: March 19, 1996
Patent Number:
5500616
An apparatus for suppressing voltage transients and detecting desaturation conditions in power transistor systems. A first transistor, usually a power transistor, has a first terminal, a second terminal, a drive terminal, and an avalanche breakdown voltage rating between the first mad second terminals. The cathode of a first diode is coupled to the first terminal of the first transistor. The first diode has a reverse breakdown voltage which is less than the avalanche breakdown voltage…
High frequency MOS device
Granted: January 23, 1996
Patent Number:
5486715
A high frequency power MOS device (90) that is built by MOS technology having high speed switching capability. The device provides improved turn-on and turn-off capabilities by providing gate interconnects comprising substantially metallization, thereby reducing parasitic resistance and capacitance. The device may be fabricated by a MOS process relying upon a dual metallization layer (127, 133) for forming the interconnects. The dual metallization layer has substantially less resistivity…
Circuit for providing isolation between components of a power control system and for communicating power and data through the isolation media
Granted: June 13, 1995
Patent Number:
5424709
An industrial automation system using transformers for providing electrical isolation between a system interface chip and a load interface chip while simultaneously allowing communication of power and data across the isolation barrier. Clock pulses are transmitted from the system interface chip to the load interface chip across one transformer, and the clock pulses are used by the load interface chip to create a power supply for operating the components within the chip. Data is…
MOS-controlled thyristor with non-planar geometry
Granted: May 2, 1995
Patent Number:
5412227
A non-planar MOS-controlled thyristor (MCT) which improved turn-off capabilities. The unique non-planar geometry brings the MOS channel region closer to the active thyristor junction, thereby reducing an "effective" resistance which inhibits turn-off of prior art devices 10. This effective resistance is a combination of the resistance through the MOS and the parasitic resistance between the MOS and active thyristor junction. For efficient thyristor turn-off at high current, the effective…
Insulated gate thyristor with gate turn on and turn off
Granted: January 10, 1995
Patent Number:
5381025
An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed…
Temperature sensing device for use in a power transistor
Granted: August 17, 1993
Patent Number:
5237481
A semiconductor diode array monolithically integrated onto a power MOS transistor or power IGBT for temperature sensing. With the application of a positive bias and a constant current, the diode array provides a voltage that varies linearly as a function of temperature for the power transistor. The diode array is constructed in such a manner so as to prevent latch-up (i.e. where a parasitic silicon controlled rectifier is turned on, locking the power transistor in an on condition) and…
Current limiting method and apparatus
Granted: March 2, 1993
Patent Number:
5191279
A method and apparatus for providing a substantially constant current from a voltage source. The apparatus includes a depletion mode transistor connected to a parallel network of resistors. At least one of the resistors is provided with a series fusible link so as to enable removal of one or more of the resistors from the network and adjust the output of the current limiter to a desired value.
Single diffusion process for fabricating semiconductor devices
Granted: February 16, 1993
Patent Number:
5187117
A simplified process of making an insulated gate transistor entails forming the active regions in a single diffusion step. The method includes the steps of implanting and diffusing impurities of a first conductivity type (p for n-channel devices), implanting and diffusing a heavy dose of impurities of the same conductivity type (p+ for n-channel devices), and implanting and diffusing impurities of the other conductivity type (n+ for n-channel devices), wherein the three types of…
Insulated gate device with current mirror having bi-directional capability
Granted: October 27, 1992
Patent Number:
5159425
A technique for providing dual direction current sensing with a single current mirror configured to provide the same current ratio in both directions for at least one predetermined temperature. The invention contemplates any of a number of techniques for providing relatively increased diode conduction in the mirror in order to provide the same current ratio as when channel conduction is the sole mechanism. These include increasing the doping of the cell body, increasing the diode area…
Multi-lead hermetic power package with high packing density
Granted: April 21, 1992
Patent Number:
5107074
An hermetic package for power semiconductor devices is disclosed. The package includes a generally rectangular cavity with leads extending through the walls thereof. The bottom of the cavity is defined by a base which includes a pair of mounting tabs protruding from opposite corners thereof. The mounting tabs are configured to allow the packages to be nested together. A cover attached to the walls provides a hermetically sealed package.
